Parallel compilation in importVerilog/MooreToCore pipeline

[thomasnormal]

Problem

The importVerilog() → MooreToCore lowering pipeline is single-threaded. For large designs (100K+ lines of SV), compilation takes several seconds. MLIR has infrastructure for parallel pass execution that could reduce this.

Current pipeline (single-threaded)

importVerilog()                    // slang parse + SV → Moore IR
populateVerilogToMoorePipeline()   // Moore optimizations
populateMooreToCorePipeline()      // Moore → LLHD+HW+Comb

Potential parallelism

• Module-level parallelism: Different modules could be lowered independently (MooreToCore operates module-by-module)
• MLIR pass manager: Supports OpPassManager::nest() with thread-safe execution when passes declare proper operation isolation
• slang parsing: Already relatively fast; the bottleneck is the MLIR lowering

Considerations

• MooreToCore.cpp is 23K+ lines — threading it requires careful analysis of shared state
• Global state (vtables, static properties) would need synchronization
• May be more practical to parallelize at the module granularity rather than within a single module
• MLIR's pass infrastructure handles most of the threading mechanics if passes are properly isolated