From 988d36c9defde6f1f96c068d9764599291561aad Mon Sep 17 00:00:00 2001 From: Casper Date: Wed, 4 Mar 2026 15:46:38 +0100 Subject: [PATCH] [sv] Enhance task function description with clock and delay usage Added explanations for using clock edges with delays in tasks, including potential simulation hang issues and recommended practices for ensuring synchronization with the virtual interface clock. This improves clarity for users implementing task functions in SystemVerilog. --- src/lessons/sv/tasks-functions/description.html | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/lessons/sv/tasks-functions/description.html b/src/lessons/sv/tasks-functions/description.html index d281958..0040949 100644 --- a/src/lessons/sv/tasks-functions/description.html +++ b/src/lessons/sv/tasks-functions/description.html @@ -15,6 +15,8 @@ Calling a task write_word(addr, data) is blocking. If you want to "spawn and forget" you can use fork.

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Clock and delay together. Sometimes you need both an edge and a small delay: e.g. @(posedge clk); #1; waits for the rising edge, then advances 1 time unit so that combinational outputs and setup are settled before you drive or sample signals. That pattern keeps stimulus and sampling aligned with the clock while avoiding glitches at the edge.

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Simulation hang disclaimer. In some environments, using @(posedge clk); #1; (or similar) in a task can cause the simulation to hang or run indefinitely — for example when the clock seen by the testbench is not the same as the one driving the DUT. If that happens, use the clock from the virtual interface instead: @(posedge vif.clk) (and if needed @(posedge vif.clk); #1;), so that your waits are tied to the same clock the interface and DUT use.

Your task: In tb.sv implement the three routine stubs: