Assembly.txt

              DATA    SIZES
              =============

Bit: 0 or 1
Byte: 8 bits
Word: 16 bits
Dword (Intel)/Long (ATT): 32 bits
Qword (Intel)/Quad (ATT): 64 bits


          GENERAL    SYNTAX
          =================

  INTEL                ATT
mov al, 23           movb $23, %al
mov bl, 6            movb $6, %bl
add al, bl           addb %bl, %al

- Suffix: b = byte; w = word; l = long; q = quad

ATT is more "intuitive" syntax and here is why.

In Intel syntax, destination is usually first operand. In ATT, destination
is 2nd operand. Hence, reading the syntax becomes intuitive.

Ex:
  INTEL                ATT
mov eax, 100          movl $100, %eax

ATT can be read as "Move 100 to eax"
Intel can be read as "Move in to eax value 100"

- In ATT syntax if no suffix is present to a mnemonic then the size is
  inferred from destination operand.


           x86 Register Set
           ================

AL = 8 bit register. Can hold signed & unsigned ints or single byte chars.
AH = Same as AL
AX = AH + AL. Changing values in AH and AL will affect AX, but AL and AH
are independent. H & L represent High and Low.

                     AX (ASCII register ??)
              +------+------+
              |  AH  |  AL  |
              +------+------+


EAX = 32 bit register. Lower 16 bits is AX. There is no way to directly
access top 16 bits of EAX.

                    EAX (Extra AX)
              +------+------+------+------+
              |      |      |     AX      |
              |      |      |  AH  |  AL  |
              +------+------+------+------+


RAX = 64 bit register.

                                     RAX (64 bit)
              +------+------+------+------+------+------+------+------+
              |      |      |      |      |            EAX            |
              |      |      |      |      |      |      |     AX      |
              |      |      |      |      |      |      |  AH  |  AL  |
              +------+------+------+------+------+------+------+------+


- In x64 CPU, there are 16 such registers as RAX. Its called General
  Purpose Registers (GPR).

  64     low 32     low 16      low 8             Notes
  bits     bits       bits       bits
  ------------------------------------------------------------
  RAX    EAX        AX          AH/AL             Accumulator
  RBX    EBX        BX          BH/BL             Base
  RCX    ECX        CX          CH/CL             Counter
  RDX    EDX        DX          DH/DL             Data
  RSP    ESP        SP          SPL               Stack Pointer
  RBP    EBP        BP          BPL               Base Pointer
  RSI    ESI        SI          SIL               Source Index
  RDI    EDI        DI          DIL               Destination Index

  R7     R7D        R7W         R7B               Only on 64 bit
  R8     R8D        R8W         R8B               Only on 64 bit
  R9     R9D        R9W         R9B               Only on 64 bit
  R10    R10D       R10W        R10B              Only on 64 bit
  R11    R11D       R11W        R11B              Only on 64 bit
  R12    R12D       R12W        R12B              Only on 64 bit
  R13    R13D       R13W        R13B              Only on 64 bit
  R14    R14D       R14W        R14B              Only on 64 bit
  R15    R15D       R15W        R15B              Only on 64 bit
  ------------------------------------------------------------


- There are Special Registers:
        RIP = Instruction Pointer. Location in RAM where next instruction
              is present.
        RFLAGS = Helps to check condition/results of previous instruction.
        S[] = Set of registers used by floating point unit (called x87
        floating unit). They are 80 bits wide and work like a stack.
        SIMD = Many SIMD registers, depending on CPU.
        - Many registers specific to CPU such as: counting clock ticks,
          measuring performance of branching, segment regs, etc.

- CS - Code Segment Register
  DS - Data Segment
  SS - Stack Segment
  ES - Extra

  The above 4 registers are no longer in x64, but were there earlier.

            BASIC   INSTRUCTIONS
            ====================
- mov, add, sub, inc, dec, neg, imul, ret


- C and C++, each have their own calling conventions.
- In x64, the first 6 integer variables (function parameters) is passed
  via registers. Pretty much anything that can be represented as integer
  variable is passed via registers.

         Param        Register
         -----        --------
             1        RDI
             2        RSI
             3        RCX
             4        RDX
             5        R8
             6        R9
            >6        passed on Stack

   Ex:      void Func(int a, char b, unsigned long c)
            int a: passed in EDI portion of RDI register
            char b: passed in SIL portion of RSI register
            unsigned long c: passed in RCX

- Integer values are returned in C++ in RAX registers.
         Type         Register
         ----         --------
        char/bool     AL
        short         AX
        int           EAX
        long          RAX


MEMORY ADDRESSING MODES (for x86)
(a) Indirect        (R)         Mem[Reg(R)]
        Ex: movl  (%ecx), %eax
(b) Displacement    D(R)        Mem[Reg(R)+D]
        Ex: movl  8(%ebp), %edx
(c) Complete Memory Addressing Mode. The most general form:
        D(Rb, Ri, S) = Mem[Reg(Rb) + S*Reg(Ri) + D]
        Ex: leal instructions use this
            leal (%eax, %ebx, 4), %ecx
(d) PC Relative Addressing.
        0x100   cmp r2, r3
        0x102   je  0x70        # PC relative addressing
        0x104   ...
        ...     ...
        0x172   add r3, r4

        PC relative addressing are relocatable. Absolute branches are not.

More on Addressing Modes:
-------
+ Direct Addressing (or Absolute Addressing)
+ Immediate Addressing
+ Register (Direct) Addressing
+ Register (Indirect) Addressing


DIRECT (or ABSOLUTE) ADDRESSING
----
The operand is in memory. Address of the operand is held in instruction.

            instruction
                ---
    operation, <register>, <memory-location>
                                    |
                                    |
                                    +-----> memory-location
                                              +---------+
                                              | Operand |
                                              +---------+
Ex:
    ld, r2, (100)   ; r2 = contents of memory. Address is 100

    instruction
       ---
    +---------------+
    | ld | r2 | 100 |
    +---------------+        Memory
            |    |          +-------+
            |    |          |       |
            |    |          +-------+
            |    +----> 100 |       |-----------+
            |               +-------+           |
            |               |       |           |
            |               +-------+           |
            |                                   |
            |                Registers          |
            |               +----------+        |
            |           r1  |          |        |
            |               +----------+        |
            +---------> r2  |          |<-------+
                            +----------+
                        r3  |          |
                            +----------+
                                ...


Another example of Direct (or Absolute) Addressing

Ex:
    st, r2, (100)   ; r2 = contents of memory. Address is 100

    instruction
       ---
    +---------------+
    | st | r2 | 100 |
    +---------------+        Memory
            |    |          +-------+
            |    |          |       |
            |    |          +-------+
            |    +----> 100 |       |<----------+
            |               +-------+           |
            |               |       |           |
            |               +-------+           |
            |                                   |
            |                                   |
            |                Registers          |
            |               +----------+        |
            |           r1  |          |        |
            |               +----------+        |
            +---------> r2  |          |--------+
                            +----------+
                        r3  |          |
                            +----------+
                                ...



IMMEDIATE ADDRESSING
----
The operand is held in the instruction.

            instruction
                ---
    operation, <register>, <operand>

Ex: mov r2, 123     ; r2=123

    instruction
       ---
    +---------------+
    |mov | r2 | 123 |---------------------------+
    +---------------+                           |
            |                                   |
            |                Registers          |
            |               +----------+        |
            |           r1  |          |        |
            |               +----------+        |
            +---------> r2  |          |<-------+
                            +----------+
                        r3  |          |
                            +----------+
                                ...

+ Useful for constants: int x = 123;

    C code                      Assembly code
    ------                      -------
    int x = 123;                mov r1, 123
    a = b+34;                   add r3, r4, 34  ; r3 is a, r4 is b


REGISTER DIRECT ADDRESSING
----
The operand is held in a register, which is specified in instruction.

            instruction
                ---
    operation, <register>, <register-no>
                                |
                                |
                                v
                            register-no
                            +---------+
                            | Operand |
                            +---------+

Ex: mov r3, r2      ; r3=r2

    instruction
       ---
    +---------------+
    |mov | r3 | r2  |
    +---------------+

                             Registers
                            +----------+
                        r1  |          |
                            +----------+
                        r2  |    |     |
                            +----|-----+
                        r3  |    v     |
                            +----------+
                                ...

+ Useful for integer variables.
        C Code              Assembly
        ------              --------
        x = y;              mov r1, r2
        a = b+c             mov r3, r4, r5



REGISTER INDIRECT ADDRESSING
----
The operand is held in memory. The address of operand location is held in a
register, that is specified in instruction.

            instruction
                ---
    operation, <register>, <register-no>
                                |
                                |
                                v
                            register-no
                            +---------+
                            |  Memory |
                            | Address |
                            +---------+
                                |
                                |
                                v
                            Memory Address
                            +-----------+
                            | Operand   |
                            +-----------+


Ex:     ld, r3, (r2)        ; r3=contents of memory, address in r2

    +---------------+
    | ld | r3 |(r2) |
    +---------------+        Memory
            |    |          +-------+
            |    |          |       |
            |    |          +-------+
            |    |          |   *   |100 <------+
            |    |          +---|---+           |
            |    |          |   |   |           |
            |    |          +---|---+           |
            |    |              |               |
            |    |              +----------+    |
            |    |                         |    |
            |    |           Registers     |    |
            |    |          +----------+   |    |
            |    |      r1  |          |   |    |
            |    |          +----------+   |    |
            |    +----> r2  |  100     |---|----+
            |               +----------+   |
            +---------> r3  |          |<--+
                            +----------+
                                ...


    C Code                              Assembly Code
    ------                              -------------
    int *b
    int a; // say address of a is 100
    b = &a;                             mov r1, 120
    *b = 123;                           ld  (r1), 123


REGISTER INDIRECT ADDRESSING PLUS OFFSET
----
Similar to above except an offset held in the instruction is added to register
contents to form the effective address.

            instruction
                ---
    operation, <register>, <register-no>, offset
                                |           |
                                |           |
                                v           |
                            register-no     |
                            +---------+     |
                            |  Memory |-----+
                            | Address |     |
                            +---------+     |
                                            |
                                            |
                                            v
                                    Memory Address
                                    +-----------+
                                    | Operand   |
                                    +-----------+

Ex: ld, r3, 100(r2)


REGISTER INDIRECT ADDRESSING VARIATION
(Index Register Addressing)
-----
+ Register Indirect Addressing in which register is seen as an "index" in to a
list (1D array).

+ Register holds number of locations from starting point. Starting point given
in instruction.



- Some Arithmetic Ops

      Instr     S, D    Result
     --------------------------
      addl      S, D    D = D+S
      subl      S, D    D = D-S
      imull     S, D    D = D*S
      sall      S, D    D = D<<S
      sarl      S, D    D = D>>S  # Arithmetic shift
      shrl      S, D    D = D>>S  # Logical shift
      xorl      S, D    D = D^S
      andl      S, D    D = D&S
      orl       S, D    D = D|S

   + There is no distiction between signed and unsigned numbers in
   Assembly.

- Jump instructions

      jX         Condition              Description
      ---------------------------------------------
      jmp        1                      Unconditional
      je         ZF                     Equal/Zero
      jne        ~ZF                    Not Equal/Not Zero
      js         SF                     Negative
      jns        ~SF                    Nonnegative
      jg         ~(SF^OF) & ~ZF         Greater (Signed)
      jge        ~(SF^OF)               Greater or Equal (Signed)
      jl         (SF^OF)                Less (Signed)
      jle        (SF^OF) | ZF           Less or Equal (Signed)
      ja         ~CF & ~ZF              Above (Unsigned)
      jb         CF                     Below (Unsigned)

- Status registers (implicitly set, most of instructions):
        CF = Carry Flag, only for unsigned
        ZF = Zero Flag
        SF = Sign Flag, only for signed
        OF = Overflow Flag

Conditionals: x86-64 (Performance Improvement using `cmovle` instruction)
    int absdiff(int x, int y)      |  # function prologue
    {                              |  movl %edi, %eax    # eax = x
            int res;               |  movl %esi, %edx    # edx = y
            if (x > y)             |  subl %esi, %eax    # eax = x-y
                    res = x-y;     |  subl %edi, %eax    # edx = y-x
            else                   |  cmpl %esi, %edi    # x:y
                    res = y-x;     |  cmovle %edx, %eax  # eax = edx, if <=
            return res;            |  ret
    }


+ Jump Tables:
        - Represents switch statements in C. Indirect addressing is used.
        - Doesn't show up in disassembled code.
        - Can inspect using GDB
                db asm-cntl
        - Preferred if the range of cases are small.


+ Program Stack [from 5]

R = Readable; O = Read-Only; W = Writeable; X = Executable

        +-----------------------------------+
   RW   |             STACK                 |   |
        +-----------------------------------+   | grows down
        |                                   |   |
        |                                   |   v
        |                                   |
        |                                   |
        +-----------------------------------+
   RW   |     HEAP (Dynamic Data)           | malloc()
        +-----------------------------------+
   RW   |   Static Data & Global Vars       |
        +-----------------------------------+
   O    |        String Literals            |
        +-----------------------------------+
   OX   |     Program Instructions          |
        +-----------------------------------+


+ Stack Overview

        +-----------+ <--+
        |           |    |
        |           |    |
        |           |   Caller
        +-----------+   Frame
        |  Args     |    |
        +-----------+    |
        | Ret Addr  |    |
        +-----------+ <--+
        | old %ebp  |
        +-----------+
        |           |
        | saved regs|
        |    +      |
        |  local    |
        | variables |
        +-----------+
        |   Args    |
        |  build    | Stack Pointer
        +-----------+ <---%esp


+ Register saving conventions (IA32/Linux):
        - Caller saves following registers if its being used after call to
          another routine: %eax, %edx, %ecx
        - Callee saves following registers if it wants to use them: %ebx,
          %esi, %edi
        - %eax is used to return integer value.
        - %esp, %ebp: special form of callee save-restored to original
          values upon exit from procedure.

+ X64-64 Procedure Call Highlights
 - Arguments (up to first 6) are in registers.
 - Local vars also in registers if there is room.
 - callq instruction stores 64-bit return address on stack.
 - No frame pointer (%ebp):
        - All references to stack frame made relative to %rsp. Eliminates
          need to update %ebp/%rbp, which is now available for general
          purpose use.
 - Functions can access memory up to 128 bytes beyond %rsp: the "red zone"
   - Can store some temps on stack without altering %rsp
 - Registers still designated "caller saved" or "callee saved"
 - Ideally, x86-64 functions need no stack frame at all !!!!!!!
        - Just a return address is pushed on to the stack.
 - A func does need a stack frame when it:
        - Has too many local vars
        - Has local vars that are arrays or structs
        - Uses & operator to compute address of local var
        - Calls another function that takes more than 6 args
        - Needs to save the state of callee-save regs b4 modifying them.



        Cache Performance Metrics
        =========================
Miss Rate:
        - Fraction of memory references NOT found in cache
          (misses/accesses) = (1 - hit rate)
        - Typical numbers = 3% to 10% for L1 cache

Hit Time:
        - Time to deliver a line in the cache to the processor. Includes
          time to determine if line is in the cache.
        - Typical hit times: 1-2 clock cycles for L1 cache.

Miss Penalty:
        - Additional time required because of a miss.
        - Typically 50 - 200 cycles.


                Memory Hierarcy
                ===============

                registers
                    |
                on-chip L1
                cache (SRAM)
                    |
                off/on-chip L2
                cache (SRAM)
                    |
                main memory
                 (DRAM)
                    |
                local secondary
                 storage
                    |
                remote disks


Example: Intels Core i7 Cache Hierarchy

        Core 0                          Core 1
        ------                          ------
        registers                       registers
           |                                |
     +-----+-----+                    +-----+-----+
     |           |                    |           |
     v           v                    v           v
    L1           L1                  L1           L1
  d-cache      i-cache             d-cache       i-cache
     |           |                    |            |
     L2 unified cache                 L2 unified cache
           |                                 |
           |                                 |
           L3 unified cache, shared by all cores
                             |
                             |
                        Main Memory

+ L1 i-cache and d-cache:
        32KB, 8-way set-associative, Access: 4 cycles
+ L2 unified cache:
        256KB, 8-way set-associative, Access: 11 cycles
+ L3 unified cache:
        8MB, 16-way, Access: 30-40 cycles
+ Block Size: 64 Bytes for all caches.


        Cache Organization
        ==================
+ Where will data go in cache?
        (a) Direct Mapped Caching: Data in memory is directly mapped to
        location in cache.
        (b) Fully Associative Caching: Data in memory can go anywhere in
        cache.
        (c) Set-Associative Caching: Cache is divided in to fixed number
        of sets. Data can go anywhere in those sets.

+ Layout of Set-Associative Caching:
        +-------------+------------+----+
        |             |            |    |
        +-------------+------------+----+
            (Tag)        (Index)    (Offset)

        Offset - Location of data inside a set.
        Index  - Indicates which set.
        Tag -    Type of data in Cache.

+ K-way associativity means, in EACH set in the cache, there are K
  entries to fill. So, number of sets in a Cache = (M/K) where M is size
  of Cache.

+ General Cache Organization:
        - There are S sets in a cache (2^s, where small 's' indicates
          # of bits representing sets).
        - Each set has E blocks (or cache lines) = 2^e where small 'e'
          indicates # of bits representing blocks or cache lines.
        - Each block or cache line has: V (a valid bit), Tag (certain # of
          bits indicating data type), B bytes of data (2^b, where b = # of
          bits).
        - Size of Cache = S * E * B bytes

+ When processor gets an address, it does following:
        - Locate Set.
        - Check if any line in the Set has matching tag.
                - Yes + Valid bit set = Hit
                - Else miss.
        - Locate data starting at offset.


+ How are writes handled in Cache?
        - Write-Through: write immediately to main memory.
        - Write-Back: Defer write to main memory until line is evicted.
                Need a dirty bit to indicate if line is different than
                main memory.
        - Write-Allocate: Load data in to Cache and update line in cache.
                Good if more writes to the location follow.
        - No-Write-Allocate: Just write immediately to memory.


+ Types of Cache Misses: CCC
        - Compulsory
        - Conflict
        - Capacity


+ Exceptions: Synchronous and Asynchronous.
        - Asynchronous: Occurs due to events outside processor control.
                        Interrupts are an example.
        - Synchronous:
                - Traps: Intentional transfer control of OS to perform
                  some function. Ex: Sys calls, breakpoints.
                - Faults: Unintentional but possibly recoverable. Ex: Page
                  Faults (recoverable), Segment Faults (unrecov),
                  Divide/Zero (unrecov).
                - Aborts: Unintentional and unrecoverable.

+ MMU (Memory Management Unit) uses PTBR (Page Table Base Register) to
locate the start of Page Table. MMU uses Page Table to look up and convert
Virtual Addresses to Physical Addresses.

+ Page Tables can be stored in Cache/Memory. But that can slow down Page
Table lookup's. Hence, TLB (Translation Lookaside Buffer) to speed Page
Table Lookup's. On Intel Core2 Duo, there can be 128 or 256 entries in
TLB.


        Dynamic Memory Allocation
        =========================
+ sbrk() syscall is used by malloc/calloc family of routines to increase,
decrease or allocated memory from heap.

+ What info is needed by memory allocator to keep track of blocks in heap?

+ When calling free(void *p), how does free know the size to free?
        - Keep size info in previous word. Standard practice.

+ How to keep track of free blocks?
        Method 1: Implicit Lists: Linked list of blocks (first word being
        length) - links ALL blocks, even the used blocks.
        Method 2: Explicit Lists: Linked list of free blocks.
        Method 3: Segregated free lists: Different free lists for
        different size classes.
        Method 4: Blocks sorted by size: Can use a balanced tree (R-B
        Tree) with pointers within each free block, and the length used as
        key.

+ How to keep track if block is allocated or not?
        - Standard trick to save memory. If blocks are aligned, the first
          word is size (typically, multiples of 8 bytes).
        - The last bit of these sizes are always 0. Use it to determine
          allocated/free flag.
        - When reading size, must remember to mask out this bit.

+ How to find a free block (using Implicit Lists)?
        - First fit: Search the list from beginning and return first
          match.
        - Drawbacks: Linear time, 'Splinters' at the beginning.

        - Next fit: Start from where you stopped last time. Faster than
          'First Fit' as it avoids scanning unhelpful blocks.
        - Drawback: Some research suggests that fragmentation is worse.

        - Best fit: Choose best (closest match in size) free block. This
          keeps fragementation small.
        - Drawback: Slower.




+ Common C related memory pitfalls and perils:
        1 Dereferencing bad pointers.
        2 Reading uninitialized memory.
        3 Overwriting memory.
                - bad memory assignments
                - Off-by-one error.
                - Not checking max string size (classic buffer overflow).
                - Misunderstanding pointer arithmetic.
                - Referencing a pointer instead of object it points to.

        4 Referencing non-existent variables.
                - Local variables disappear after returning from
                  functions.

        5 Freeing blocks multiple times.
        6 Referencing freed blocks.
        7 Failing to Free Blocks (Memory Leaks)
                - Returning without freeing.
                - Freeing only part of data structure.


        3 Overwriting memory

        Ex:
        --
        int **p;
        p = (int **) malloc (N * sizeof(int));
        // Incorrect. It should be sizeof(int *). Here sizeof(int) is
        // assigned, which can be 4 bytes each.

        for (i=0; i<N; i++)
                p[i] = (int *) malloc (M * sizeof(int));
                // because of above, on a 64-bit m/c, p[i] will get 8
                // bytes each, hence an overwrite of memory.


+ Data Representation in Java:
        - For Chars, 2 bytes (unlike 1 byte in C).
        - Chars are NOT null terminated.
        - Beginning of the string has length field.
        - Same as above for Arrays. First field is length of Array.


+ Data structures (Objects) in Java

        C                       Java
       ---                      ----
   struct rec {                 class Rec {
        int i;                          int i;
        int a[3];                       int[] a = new int[3];
        struct rec *p;                  Rec p;
   };                           };


   Memory Layout C                      Memory Layout Java
   ---------------                      ------------------

   +---+---------------+----+           +----+----+----+
   | i |       a       | p  |           | i  | a  | p -|--->
   +---+---------------+----+           +----+----+----+
                                               |
                                               |
                                               v
                                        +----+----------------+
                                        | 3  |   int [3]      |
                                        +----+----------------+

+ References in Java (pointers equivalent) can only point to an object.
+ And it can point only to first element (not to middle of it).



Reference:
[1]
http://www.youtube.com/watch?v=zRqLU_AxNdU&feature=share&list=PLKK11Ligqiti8g3gWRtMjMgf1KoKDOvME&index=3

[2]
http://www.youtube.com/watch?v=nDj35pMLBQE&list=PLKK11Ligqiti8g3gWRtMjMgf1KoKDOvME&index=3

[3] Complete code set for IA32
http://www.jegerlehner.ch/intel/IntelCodeTable.pdf

[4] Very good description of instructions
http://web.itu.edu.tr/kesgin/mul06/intel/index.html

[5] Notes from Hardware Software Interface course on Coursera.

[6] http://webpages.uncc.edu/abw/ITCS3182F09/slides3.pdf


@@@@@@@@@@@@@@@@@@@@@     ENDIANNESS EXPLAINED     @@@@@@@@@@@@@@@@@@@@@@@@@

Consider four byte number: 0x0a0b0c0d; left being smallest memory address
and right being highest.

  Number: 0x0a0b0c0d. Here LSB is 0x0d and MSB is 0x0a

  Memory Address: 0x100    0x101    0x102    0x103
                  +--------+--------+--------+--------+
                  |        |        |        |        |
                  +--------+--------+--------+--------+

Little-Endian: In LE, LSB is in lowest memory and MSB in highest memory
address. So, the number is stored as: 0x0d0c0b0a in memory.
Ex: Intel x86

  Number: 0x0a0b0c0d. Here LSB is 0x0d and MSB is 0x0a

  Memory Address: 0x100    0x101    0x102    0x103
                  +--------+--------+--------+--------+
                  |  0x0d  |  0x0c  |  0x0b  |  0x0a  |
                  +--------+--------+--------+--------+

  code:
        int i = 0x0a0b0c0d;
        char *c = (char *) &i;
        printf ("0x%x\n", *c);

        // Output is 0xd = little-endian.

Big-Endian (aka Network Byte Order): In BE, MSB is in lowest memory address
and LSB in highest. It looks the way numbers are written down on paper.
So, the number is stored as: 0x0a0b0c0d in memory.
Ex: Motorola 68k, Data transfer on networks use NBO,

  Number: 0x0a0b0c0d.

  Memory Address: 0x100    0x101    0x102    0x103
                  +--------+--------+--------+--------+
                  |  0x0a  |  0x0b  |  0x0c  |  0x0d  |
                  +--------+--------+--------+--------+

  code:
        int i = 0x0a0b0c0d;
        char *c = (char *) &i;
        printf ("0x%x\n", *c);

        // Output is 0xa = big-endian.

Host-Byte Order: Ordering on the host machine. If processor is x86, its
little-endian, if its Motorola's 68k, its big-endian.

Mixed-Endian (or Middle-Endian): Ordering of bytes within 16-bit word may differ
from ordering of 16-bit words within 32-bit word.

Bi-Endian: Architectures allowing switchable endianness in data segment, code
segment or both. 'Bi-Endian' refers how processor accesses data. Instruction
access (fetching instruction words) is usually fixed endian. Intel's Itanium CPU
allows bi-endian data and instruction access.
Ex: ARM version 3 and above, PowerPC,

Reference:
[1] http://en.wikipedia.org/wiki/Endianness


@@@@@@@@@@@@@@@@  C TO ASSEMBLY CODE GENERATION & OTHER TOOLS @@@@@@@@@@@@@@@@@@
$ gcc -c -S test.c
/* generates a test.s assembly file */

$ gcc -g -c test.c
/* generates test.o object file, with debug symbols present (-g flag) */

$ objdump
$ readelf
$ nm
$ strings
$ size <object or exec file>

@@@@@@@@@@@@@@@@@@@@@@@@@@@@@  readelf commands @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@

/* header info */
$ readelf --file-header <elf-file>

Ex:
$ readelf --file-header vim.core
ELF Header:
  Magic:   7f 45 4c 46 02 01 01 09 00 00 00 00 00 00 00 00
  Class:                             ELF64
  Data:                              2's complement, little endian
  Version:                           1 (current)
  OS/ABI:                            UNIX - FreeBSD
  ABI Version:                       0
  Type:                              CORE (Core file)
  Machine:                           Advanced Micro Devices X86-64
  Version:                           0x1
  Entry point address:               0x0
  Start of program headers:          64 (bytes into file)
  Start of section headers:          0 (bytes into file)
  Flags:                             0x0
  Size of this header:               64 (bytes)
  Size of program headers:           56 (bytes)
  Number of program headers:         79
  Size of section headers:           64 (bytes)
  Number of section headers:         0
  Section header string table index: 0

/* notes sections of elf-files have more info about the file (like .core files) */
$ readelf --notes <elf-file>

Ex:
$ readelf --notes vim.core

Notes at offset 0x00001188 with length 0x0000ad18:
  Owner         Data size       Description
  FreeBSD       0x00000078      NT_PRPSINFO (prpsinfo structure)
  FreeBSD       0x000000e0      NT_PRSTATUS (prstatus structure)
  FreeBSD       0x00000200      NT_FPREGSET (floating point registers)
  FreeBSD       0x00000018      NT_THRMISC (thrmisc structure)
  FreeBSD       0x000000e0      NT_PRSTATUS (prstatus structure)
  FreeBSD       0x00000200      NT_FPREGSET (floating point registers)
  FreeBSD       0x00000018      NT_THRMISC (thrmisc structure)
  FreeBSD       0x00000884      NT_PROCSTAT_PROC (proc data)
  FreeBSD       0x0000156c      NT_PROCSTAT_FILES (files data)
  FreeBSD       0x00008574      NT_PROCSTAT_VMMAP (vmmap data)
  FreeBSD       0x00000008      NT_PROCSTAT_GROUPS (groups data)
  FreeBSD       0x00000006      NT_PROCSTAT_UMASK (umask data)
  FreeBSD       0x000000d4      NT_PROCSTAT_RLIMIT (rlimit data)
  FreeBSD       0x00000008      NT_PROCSTAT_OSREL (osreldate data)
  FreeBSD       0x0000000c      NT_PROCSTAT_PSSTRINGS (ps_strings data)
  FreeBSD       0x00000114      NT_PROCSTAT_AUXV (auxv data)

/* segments info. Segments are info on chunks of code from various files that a
 * process/binary includes. */
$ readelf --segments <elf-file>


@@@@@@@@@@@@@@@@@@@@@@@       UDEMY's ASSEMBLY    ADVENTURES     @@@@@@@@@@@@@

FASM (Flat Assembler) Instructions
---

First Instructions

mov dst, src    ; move contents of source to destination
add dst, src    ; dst = dst + src
sub dst, src    ; dst = dst - src = dst + (-src), 2's complement
                ; in 'add' and 'sub', dst can wrap around. Wrap around is done
                ; as per arg size. So, if there's a carry over, it's dropped.


Arithmetic Instructions

inc dst     ; increment dst by 1. Wrap around can happen.
dec dst     ; decrement dst by 1. Underflow is possible.
mul arg     ; multiply numbers (unsigned numbers)

arg is of following forms
    ax = al * arg           ; if arg is of size 8 bits
    dx:ax = ax * arg        ; if arg is of size 16 bits
    edx:eax = eax * arg     ; if arg is of size 32 bits
                            ; there's a 64 bit version too

dx:ax mean concatenation of bits in dx and ax registers

Examples:

mul ecx         ; multiply eax and ecx and store in edx:eax
mul si          ; dx:ax = ax * si
mul al          ; ax = al * al
mul 2Ah         ; Invalid although there's no strong reason. Probably
                ; historical reasons


div arg         ; Divides one number by another number (unsigned division)

arg is of following forms:
    * arg of size 8 bits:
        al = ax/arg     ; Quotient (integral division)
        ah = ax%arg     ; Remainder (integral remainder)

    * arg of size 16 bits:
        ax = dx:ax/arg  ; Quotient
        dx = dx:ax%arg  ; Remainder

    * arg of size 32 bits:
        eax = edx:eax/arg   ; Quotient
        edx = edx:eax%arg   ; Remainder

Examples:

div ch      ; Divides ax by ch and al=Quotient, ah=Remainder
div esi     ; Divides edx:eax by esi. eax=Quotient, edx=Remainder
div di      ; Divides dx:ax by di. ax=Quotient, dx=Remainder
div 5Cah    ; Invalid


Exceptions: Two possible exceptions
1) Divide by zero
2) Quotient overflow



Tools
=====
Total Commander
- File Explorer for Windows. Has some additional features to regular file
  explorer

HxD: www.mh-nexus.org
- Hex Editor. Very stable and understands many file formats (txt, exe, png and
  many more).
- Key features of Hex Editor
    * Must have ability to change # of columns
    * Must be searchable, either text or hex values
    * Copy/Paste (access to Clipboard)
    * Editable!!

Hex Workshop
- Other Hex editor. Paid.

010 Editors
- Other Hex editor. Paid.



Reference:
[1] Section 3 in:
https://gcc.gnu.org/onlinedocs/gcc-5.2.0/gcc/
[2] Info on coredump:
http://backtrace.io/blog/blog/2015/10/03/whats-a-coredump/
[3] Udemy's Assembly Adventures course