From 4d52461362e60c64452de00ead992e6c68685ce3 Mon Sep 17 00:00:00 2001 From: retrocpugeek <279159355+retrocpugeek@users.noreply.github.com> Date: Tue, 11 Aug 2026 21:30:14 +1000 Subject: [PATCH] tests: pre-translate the tb in arm_movr12_hang The 500us timeout covered code generation as well as execution, so the test flaked on the macos-14 x86_64 wheel job. Pre-build the tb and raise the timeout to 10ms to absorb scheduler stalls; a pre-built tb drops the `until` exit, so svc plus an intr hook stops emulation in-band instead. Co-Authored-By: Claude Opus 5 (1M context) --- tests/regress/arm_movr12_hang.py | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/tests/regress/arm_movr12_hang.py b/tests/regress/arm_movr12_hang.py index 528e31d943..f703934b88 100755 --- a/tests/regress/arm_movr12_hang.py +++ b/tests/regress/arm_movr12_hang.py @@ -5,11 +5,10 @@ class MovHang(regress.RegressTest): - # NOTE: This test was failing when workflow was using ubuntu-latest + qemu. Fixed once switched to native arm runner def runTest(self): uc = Uc(UC_ARCH_ARM, UC_MODE_ARM) uc.mem_map(0x1000, 0x1000) - uc.mem_write(0x1000, b'\x00\xc0\x00\xe3') # movw r12, #0 + uc.mem_write(0x1000, b'\x00\xc0\x00\xe3\x00\x00\x00\xef') # movw r12, #0 ; svc #0 def hook_block(uc, addr, *args): regress.logger.debug('enter block 0x%#06x', addr) @@ -19,10 +18,15 @@ def hook_block(uc, addr, *args): self.assertEqual(0x123, uc.reg_read(UC_ARM_REG_R12)) uc.hook_add(UC_HOOK_BLOCK, hook_block) + uc.hook_add(UC_HOOK_INTR, lambda uc, intno, data: uc.emu_stop()) uc.count = 0 - # print 'block should only run once' - uc.emu_start(0x1000, 0x1004, timeout=500) + # Translate the block up front so the timeout bounds execution only, not + # code generation. A pre-built tb does not carry the `until` exit, so the + # svc stops emulation in-band instead. The timeout is only a hang guard, + # with headroom for a scheduler stall on a loaded machine. + uc.ctl_request_cache(0x1000) + uc.emu_start(0x1000, 0x1008, timeout=10_000) self.assertEqual(0x0, uc.reg_read(UC_ARM_REG_R12)) self.assertEqual(uc.count, 1)