Fix BK bus desync: atomic TREADY in AXISBRLater

Root cause of real-FPGA hang (hw_emu unaffected):

AXISBRLater feeds bootstrapping key (BK) data to ExternalProductMiddle
via 4 AXI4-Stream register slices per polynomial half. Previously each
slice received TREADY := trgswinready(k) independently, while
trgswinvalid(k) = Cat(tvalidvec).andR (requires ALL 4 valid). When one
HBM bus momentarily stalled (TVALID=0), the other 3 slices saw
TREADY=1 and consumed their data, but TRGSWBatchMemory saw wen=0 and
discarded it. This silently corrupted the BK accumulation, causing
MULandACC to miss outflag events, finreg to stall short of its target,
and BlindRotate to hang in FINWAIT forever.

Fix: require all 4 buses to be simultaneously valid before any slice
advances (TREADY := trgswinready(k) && allValid). This is correct
because HomGate dispatches all 4 buses in lock-step; the depth-8 slices
absorb the small SLR-crossing skew.

Why hw_emu was unaffected: simulated HBM delivers all buses in
lock-step every cycle, so the AND was always 1 and the bug never fired.

Also includes diagnostic infrastructure added during investigation:
- BRBack_top.v: axis18 debug stream packs 4×8-bit saturating counters
  (feedback ch0/ch1, BK ch0/ch4 beat counts) for live hang diagnosis
- HomGate_top.v + HomGate_control_s_axi.v: 4th debug register at
  AXI-lite 0x20c captures the BRBack axis18 debug word
- xrt_regread.cpp: decode and print the new brback_dbg register with
  expected reference values in the 5-second polling output
- build_brback_xo.tcl: copy RTL sources into ip_repo/src to work
  around ipx::package_project file-copy reliability issue

Result: gate 0 = 1.32ms, gate 1 = 1.25ms, PASS on Alveo U280 @ 300MHz
Timing: WNS = 0.016ns, all constraints met, zero violations.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>

Author: nindanaoto

chisel/HomGate/src/main/scala/BlindRotate.scala

@@ -369,14 +369,22 @@ class AXISBRLater(implicit val conf:Config) extends Module{
 	for(k <- 0 until conf.k+1){
 		val tvalidvec = Wire(Vec(conf.bknumbus/2,Bool()))
 		val tdatavec = Wire(Vec(conf.bknumbus/2,UInt(conf.buswidth.W)))
-		for(i <- 0 until conf.bknumbus/2){
+		val allValid = Cat(tvalidvec).andR
+		val slices = for(i <- 0 until conf.bknumbus/2) yield {
 			val slice = Module(new AXI4StreamRegisterSlice(conf.buswidth,conf.axi4snumslice))
 			slice.io.subordinate <> io.axi4bkin(k*conf.bknumbus/2+i)
-			slice.io.manager.TREADY := extpmiddle.io.trgswinready(k)
 			tvalidvec(i) := slice.io.manager.TVALID
 			tdatavec(i) := slice.io.manager.TDATA
+			slice
+		}
+		// Slices must advance atomically: only when ALL 4 buses are simultaneously valid
+		// AND TRGSWBatchMemory is ready to accept. Without this, a momentary stall on any
+		// one HBM bus causes the other 3 slices to consume their data without writing it to
+		// TRGSWBatchMemory (silently discarding those BK beats → corrupted accumulation).
+		for(i <- 0 until conf.bknumbus/2){
+			slices(i).io.manager.TREADY := extpmiddle.io.trgswinready(k) && allValid
 		}
-		extpmiddle.io.trgswinvalid(k) := Cat(tvalidvec).andR
+		extpmiddle.io.trgswinvalid(k) := allValid
 		extpmiddle.io.trgswin(k) := Cat(tdatavec.reverse)
 	}
 

vitis/rtl/BRBack_top.v

@@ -338,9 +338,35 @@ module BRBack #(
 
   assign axis16_tkeep = {4{1'b1}};
 
-// axis18: tied off (unused)
-assign axis18_tvalid = 1'b0;
-assign axis18_tdata  = 32'b0;
+// axis18: debug counters packed into 32 bits (→ HomGate axis10 → bkin0_beats register)
+// Each byte = bits[16:9] of a 17-bit beat counter (512 beats/unit):
+// [31:24] = axis04_tvalid >>9 (feedback ch0, max 81408→0x9F; 3 short→0x9E)
+// [23:16] = axis05_tvalid >>9 (feedback ch1, same expected value)
+// [15: 8] = axis06_tvalid >>9 (BK ch0 from HomGate, max 122112→0xEE; stalled→less)
+// [ 7: 0] = axis10_tvalid >>9 (BK ch4 from HomGate, same expected value as ch0)
+reg [16:0] dbg_fb0_cnt  = 17'b0;
+reg [16:0] dbg_fb1_cnt  = 17'b0;
+reg [16:0] dbg_bk0_cnt  = 17'b0;
+reg [16:0] dbg_bk4_cnt  = 17'b0;
+always @(posedge ap_clk) begin
+    if (areset) begin
+        dbg_fb0_cnt <= 17'b0;
+        dbg_fb1_cnt <= 17'b0;
+        dbg_bk0_cnt <= 17'b0;
+        dbg_bk4_cnt <= 17'b0;
+    end else begin
+        if (axis04_tvalid && dbg_fb0_cnt != 17'h1FFFF)
+            dbg_fb0_cnt <= dbg_fb0_cnt + 1;
+        if (axis05_tvalid && dbg_fb1_cnt != 17'h1FFFF)
+            dbg_fb1_cnt <= dbg_fb1_cnt + 1;
+        if (axis06_tvalid && dbg_bk0_cnt != 17'h1FFFF)
+            dbg_bk0_cnt <= dbg_bk0_cnt + 1;
+        if (axis10_tvalid && dbg_bk4_cnt != 17'h1FFFF)
+            dbg_bk4_cnt <= dbg_bk4_cnt + 1;
+    end
+end
+assign axis18_tvalid = 1'b1;
+assign axis18_tdata  = {dbg_fb0_cnt[16:9], dbg_fb1_cnt[16:9], dbg_bk0_cnt[16:9], dbg_bk4_cnt[16:9]};
 assign axis18_tkeep  = {4{1'b1}};
 assign axis18_tlast  = 1'b0;
 

vitis/rtl/HomGate_control_s_axi.v

@@ -58,7 +58,8 @@ module HomGate_control_s_axi #(
     // Debug read-only registers
     input  wire [31:0]                     dbg_reg0,
     input  wire [31:0]                     dbg_reg1,
-    input  wire [31:0]                     dbg_reg2
+    input  wire [31:0]                     dbg_reg2,
+    input  wire [31:0]                     dbg_reg3
 );
 
     //------------------------Address Info-------------------
@@ -148,6 +149,7 @@ module HomGate_control_s_axi #(
         ADDR_DBG_REG0            = 12'h200,  // AXISIKS output beat count
         ADDR_DBG_REG1            = 12'h204,  // axis01 input beat count (SEI→HomGate)
         ADDR_DBG_REG2            = 12'h208,  // misc status bits
+        ADDR_DBG_REG3            = 12'h20c,  // BK bus0 (axis02) beat count
         WRIDLE                   = 2'd0,
         WRDATA                   = 2'd1,
         WRRESP                   = 2'd2,
@@ -363,6 +365,7 @@ module HomGate_control_s_axi #(
                     ADDR_DBG_REG0: rdata <= dbg_reg0;
                     ADDR_DBG_REG1: rdata <= dbg_reg1;
                     ADDR_DBG_REG2: rdata <= dbg_reg2;
+                    ADDR_DBG_REG3: rdata <= dbg_reg3;
                     default: rdata <= 32'b0;
                 endcase
             end

vitis/rtl/HomGate_top.v

@@ -676,7 +676,8 @@ inst_control_s_axi (
   .axi20_ptr0   ( axi20_ptr0            ),
   .dbg_reg0     ( dbg_iksout_cnt        ),
   .dbg_reg1     ( dbg_axis01_cnt        ),
-  .dbg_reg2     ( dbg_misc              )
+  .dbg_reg2     ( dbg_misc              ),
+  .dbg_reg3     ( dbg_bkin0_cnt         )
 );
 
 ///////////////////////////////////////////////////////////////////////////////
@@ -728,30 +729,36 @@ wire axi4sout_TLAST;
 wire dm00_s2mm_err;
 wire dm00_s2mm_sts_tvalid;
 
-// Debug beat counters (read via AXI-lite at 0x200/0x204/0x208)
+// Debug beat counters (read via AXI-lite at 0x200/0x204/0x208/0x20c)
 reg [31:0] dbg_iksout_cnt  = 32'b0;  // AXISIKS output beats accepted
 reg [31:0] dbg_axis01_cnt  = 32'b0;  // axis01 beats entering HomGate
 reg [31:0] dbg_misc        = 32'b0;  // latched/live status bits
+reg [31:0] dbg_bkin0_cnt   = 32'b0;  // NTT beat count from BRBack (via axis18→axis10)
 
 always @(posedge ap_clk) begin
     if (areset) begin
         dbg_iksout_cnt <= 32'b0;
         dbg_axis01_cnt <= 32'b0;
         dbg_misc       <= 32'b0;
+        dbg_bkin0_cnt  <= 32'b0;
     end else begin
         // Count AXISIKS output accepted beats (expect 40 total for 2 batches)
         if (axi4siksout_TVALID && axi4siksout_TREADY && dbg_iksout_cnt != 32'hFFFFFFFF)
             dbg_iksout_cnt <= dbg_iksout_cnt + 1;
         // Count axis01 input beats from BRBack (expect 2050 per gate)
         if (axis01_tvalid && axis01_tready && dbg_axis01_cnt != 32'hFFFFFFFF)
             dbg_axis01_cnt <= dbg_axis01_cnt + 1;
+        // Capture BRBack NTT-beat counter from axis10 (debug stream)
+        if (axis10_tvalid)
+            dbg_bkin0_cnt <= axis10_tdata;
         // Latch misc status bits (sticky once set)
         if (axi4sout_TLAST)              dbg_misc[0] <= 1'b1;  // axi4sout TLAST seen
         if (dm00_s2mm_err)               dbg_misc[1] <= 1'b1;  // S2MM error
         if (axi4outcmd_TVALID)           dbg_misc[2] <= 1'b1;  // S2MM command issued
         if (dm00_s2mm_sts_tvalid)        dbg_misc[3] <= 1'b1;  // S2MM completed
         if (axi4siksout_TVALID)          dbg_misc[4] <= 1'b1;  // IKS ever had output valid
         if (axis01_tvalid)               dbg_misc[5] <= 1'b1;  // axis01 ever had data
+        if (axi4bkin_0_TVALID)           dbg_misc[6] <= 1'b1;  // BK bus0 ever had data
         // Live (instantaneous) signals in bits 15:8
         dbg_misc[8]  <= axi4siksout_TVALID;
         dbg_misc[9]  <= axi4siksout_TREADY;

vitis/scripts/build_brback_xo.tcl

@@ -40,6 +40,12 @@ for {set i 0} {$i <= 18} {incr i} {
     ipx::associate_bus_interfaces -busif [format "axis%02d" $i] -clock ap_clk [ipx::current_core]
 }
 
+# Workaround: ipx::package_project -import_files sometimes fails to copy RTL files.
+# Manually copy sources to ip_repo/src so package_xo includes them.
+file mkdir ${ip_repo_dir}/src
+file copy -force ${rtl_dir}/BRBack_top.v ${ip_repo_dir}/src/BRBack_top.v
+file copy -force ${rtl_dir}/HomGateWrap.v ${ip_repo_dir}/src/HomGateWrap.v
+
 # Save IP
 ipx::create_xgui_files [ipx::current_core]
 ipx::update_checksums [ipx::current_core]

xcltest/HomGate/xrt_regread.cpp

@@ -154,12 +154,13 @@ int fpga_wait_kernel(int run_idx) {
                 break;
             }
             // Print AP control register and debug register diagnostics
-            uint32_t ap_ctrl = 0xDEAD, dbg0 = 0xDEAD, dbg1 = 0xDEAD, dbg2 = 0xDEAD;
+            uint32_t ap_ctrl = 0xDEAD, dbg0 = 0xDEAD, dbg1 = 0xDEAD, dbg2 = 0xDEAD, dbg3 = 0xDEAD;
             if (s_kern) {
                 try { ap_ctrl = s_kern->read_register(0x000); } catch (...) {}
                 try { dbg0   = s_kern->read_register(0x200); } catch (...) {}
                 try { dbg1   = s_kern->read_register(0x204); } catch (...) {}
                 try { dbg2   = s_kern->read_register(0x208); } catch (...) {}
+                try { dbg3   = s_kern->read_register(0x20c); } catch (...) {}
             }
             std::cout << "fpga_wait_kernel: " << elapsed << "s elapsed, ap_ctrl=0x"
                       << std::hex << ap_ctrl << std::dec
@@ -170,6 +171,12 @@ int fpga_wait_kernel(int run_idx) {
                       << " iksout_beats=" << dbg0
                       << " axis01_beats=" << dbg1
                       << " misc=0x" << std::hex << dbg2 << std::dec
+                      << " brback_dbg=0x" << std::hex << dbg3
+                      << "(fb0=" << ((dbg3>>24)&0xFF) << "/0x9F"
+                      << " fb1=" << ((dbg3>>16)&0xFF) << "/0x9F"
+                      << " bk0=" << ((dbg3>>8)&0xFF) << "/0xEE"
+                      << " bk4=" << ((dbg3>>0)&0xFF) << "/0xEE)"
+                      << std::dec
                       << std::endl;
             if (elapsed >= timeout_s) {
                 std::cerr << "fpga_wait_kernel: TIMEOUT after " << elapsed << "s" << std::endl;