As much I am aware, every Sony CMOS sensors have a power ON and power OFF sequencing mechanism, DVDD -> OVDD -> AVDD.
How are you mitigating it?
When I had a look the PCB design and schematics, there is only one EN flag, how is this sequencing really underneath?
Is there some kind of delay to be created or managed for this? or just the single flag is enough?
As much I am aware, every Sony CMOS sensors have a power ON and power OFF sequencing mechanism, DVDD -> OVDD -> AVDD.
How are you mitigating it?
When I had a look the PCB design and schematics, there is only one EN flag, how is this sequencing really underneath?
Is there some kind of delay to be created or managed for this? or just the single flag is enough?