From f9fd9fec2e0efadf44fd7a3cba887c7143e7c509 Mon Sep 17 00:00:00 2001
From: Alex Lanzano <lanzano.alex@gmail.com>
Date: Thu, 8 May 2025 16:20:06 -0400
Subject: [PATCH 1/7] Add config options for stm32f4 boards

This introduces the following configuration options to allow for easier
support for boards using the stm32f4 MCU

CLOCK_SPEED: This defines the clock speed in Hz
STM32_PLLM: This defines the PLLM parameter in the pll clock setup
STM32_PLLN: This defines the PLLN parameter in the pll clock setup
STM32_PLLP: This defines the PLLP parameter in the pll clock setup
STM32_PLLQ: This defines the PLLQ parameter in the pll clock setup
---
 options.mk | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/options.mk b/options.mk
index 8399bc33f3..0550baa643 100644
--- a/options.mk
+++ b/options.mk
@@ -948,3 +948,31 @@ ifneq ($(CERT_CHAIN_VERIFY),)
   endif
   SIGN_OPTIONS += --cert-chain $(CERT_CHAIN_FILE)
 endif
+
+# Clock Speed (Hz)
+ifneq ($(CLOCK_SPEED),)
+	CFLAGS += -DCLOCK_SPEED=$(CLOCK_SPEED)
+endif
+
+# STM32F4 clock options
+ifneq ($(STM32_PLLM),)
+	CFLAGS += -DSTM32_PLLM=$(STM32_PLLM)
+endif
+ifneq ($(STM32_PLLN),)
+	CFLAGS += -DSTM32_PLLN=$(STM32_PLLN)
+endif
+ifneq ($(STM32_PLLP),)
+	CFLAGS += -DSTM32_PLLP=$(STM32_PLLP)
+endif
+ifneq ($(STM32_PLLQ),)
+	CFLAGS += -DSTM32_PLLQ=$(STM32_PLLQ)
+endif
+
+# STM32 UART options
+ifeq ($(USE_UART1),1)
+	CFLAGS += -DUSE_UART1=1
+endif
+
+ifeq ($(USE_UART3),1)
+	CFLAGS += -DUSE_UART3=1
+endif

From 10faed06a4727df0d5e2aa0156bc575973ed412b Mon Sep 17 00:00:00 2001
From: Alex Lanzano <lanzano.alex@gmail.com>
Date: Thu, 8 May 2025 16:29:03 -0400
Subject: [PATCH 2/7] Update stm32f4 hal to use config options to setup clock
 and uart

Modifies the stm32f4 hal to use the new config options to configure the
PLL clock. This also modifies the stm32f4 uart driver to allow the user
to specify which uart they want to use via the config option.
---
 hal/stm32f4.c               |  10 +--
 hal/uart/uart_drv_stm32f4.c | 128 ++++++++++++++++++++++--------------
 2 files changed, 84 insertions(+), 54 deletions(-)

diff --git a/hal/stm32f4.c b/hal/stm32f4.c
index 82e6f125a9..981fe79de0 100644
--- a/hal/stm32f4.c
+++ b/hal/stm32f4.c
@@ -261,11 +261,11 @@ static void clock_pll_on(int powersave)
     APB1_CLOCK_ER |= PWR_APB1_CLOCK_ER_VAL;
 
     /* Select clock parameters (CPU Speed = 168MHz) */
-    cpu_freq = 168000000; (void)cpu_freq; /* not used */
-    pllm = 8;
-    plln = 336;
-    pllp = 2;
-    pllq = 7;
+    cpu_freq = CLOCK_SPEED; (void)cpu_freq; /* not used */
+    pllm = STM32_PLLM;
+    plln = STM32_PLLN;
+    pllp = STM32_PLLP;
+    pllq = STM32_PLLQ;
     pllr = 0; (void)pllr; /* not used */
     hpre = RCC_PRESCALER_DIV_NONE;
     ppre1 = RCC_PRESCALER_DIV_4;
diff --git a/hal/uart/uart_drv_stm32f4.c b/hal/uart/uart_drv_stm32f4.c
index c036c7f2af..4564371fba 100644
--- a/hal/uart/uart_drv_stm32f4.c
+++ b/hal/uart/uart_drv_stm32f4.c
@@ -29,18 +29,11 @@
 
 #include <stdint.h>
 
-/* Driver hardcoded to work on UART3 (PD8/PD9) */
-#define UART3 (0x40004800)
-#define UART3_PIN_AF 7
-#define UART3_RX_PIN 9
-#define UART3_TX_PIN 8
-
-#define UART3_SR       (*(volatile uint32_t *)(UART3))
-#define UART3_DR       (*(volatile uint32_t *)(UART3 + 0x04))
-#define UART3_BRR      (*(volatile uint32_t *)(UART3 + 0x08))
-#define UART3_CR1      (*(volatile uint32_t *)(UART3 + 0x0c))
-#define UART3_CR2      (*(volatile uint32_t *)(UART3 + 0x10))
-
+/* Common UART Config */
+#if !defined(USE_UART1) && !defined(USE_UART3)
+#define USE_UART3
+#endif
+#define UART_PIN_AF 7
 #define UART_CR1_UART_ENABLE    (1 << 13)
 #define UART_CR1_SYMBOL_LEN     (1 << 12)
 #define UART_CR1_PARITY_ENABLED (1 << 10)
@@ -51,52 +44,89 @@
 #define UART_SR_TX_EMPTY        (1 << 7)
 #define UART_SR_RX_NOTEMPTY     (1 << 5)
 
-
+#ifndef CLOCK_SPEED
 #define CLOCK_SPEED (168000000)
+#endif
+
+/* Common GPIO Config */
+#define GPIO_MODE_AF (2)
 
-#define APB1_CLOCK_ER           (*(volatile uint32_t *)(0x40023840))
-#define UART3_APB1_CLOCK_ER_VAL 	(1 << 18)
+/* UART1 Config */
+#ifdef USE_UART1
+#define UART_RX_PIN 7
+#define UART_TX_PIN 6
+
+#define UART1 (0x40011000)
+#define UART_SR       (*(volatile uint32_t *)(UART1))
+#define UART_DR       (*(volatile uint32_t *)(UART1 + 0x04))
+#define UART_BRR      (*(volatile uint32_t *)(UART1 + 0x08))
+#define UART_CR1      (*(volatile uint32_t *)(UART1 + 0x0c))
+#define UART_CR2      (*(volatile uint32_t *)(UART1 + 0x10))
+
+#define UART_CLOCK_ER           (*(volatile uint32_t *)(0x40023844))
+#define UART_CLOCK_ER_VAL 	(1 << 4)
+
+#define GPIO_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
+#define GPIO_CLOCK_ER_VAL (1 << 1)
+#define GPIOB_BASE 0x40020400
+#define GPIO_MODE  (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
+#define GPIO_AF    (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
+#endif
+
+/* UART3 Config */
+#ifdef USE_UART3
+#define UART_RX_PIN 9
+#define UART_TX_PIN 8
 
-#define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
-#define GPIOD_AHB1_CLOCK_ER (1 << 3)
+#define UART3 (0x40004800)
+#define UART_SR       (*(volatile uint32_t *)(UART3))
+#define UART_DR       (*(volatile uint32_t *)(UART3 + 0x04))
+#define UART_BRR      (*(volatile uint32_t *)(UART3 + 0x08))
+#define UART_CR1      (*(volatile uint32_t *)(UART3 + 0x0c))
+#define UART_CR2      (*(volatile uint32_t *)(UART3 + 0x10))
+
+#define UART_CLOCK_ER           (*(volatile uint32_t *)(0x40023840))
+#define UART_CLOCK_ER_VAL 	    (1 << 18)
+
+#define GPIO_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
+#define GPIO_CLOCK_ER_VAL (1 << 3)
 #define GPIOD_BASE 0x40020c00
-#define GPIOD_MODE  (*(volatile uint32_t *)(GPIOD_BASE + 0x00))
-#define GPIOD_AFL   (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
-#define GPIOD_AFH   (*(volatile uint32_t *)(GPIOD_BASE + 0x24))
-#define GPIO_MODE_AF (2)
+#define GPIO_MODE  (*(volatile uint32_t *)(GPIOD_BASE + 0x00))
+#define GPIO_AF    (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
+#endif
+
 
 static void uart_pins_setup(void)
 {
     uint32_t reg;
-    AHB1_CLOCK_ER |= GPIOD_AHB1_CLOCK_ER;
+    GPIO_CLOCK_ER |= GPIO_CLOCK_ER_VAL;
     /* Set mode = AF */
-    reg = GPIOD_MODE & ~ (0x03 << (UART3_RX_PIN * 2));
-    GPIOD_MODE = reg | (2 << (UART3_RX_PIN * 2));
-    reg = GPIOD_MODE & ~ (0x03 << (UART3_TX_PIN * 2));
-    GPIOD_MODE = reg | (2 << (UART3_TX_PIN * 2));
-
-    /* Alternate function: use high pins (8 and 9) */
-    reg = GPIOD_AFH & ~(0xf << ((UART3_TX_PIN - 8) * 4));
-    GPIOD_AFH = reg | (UART3_PIN_AF << ((UART3_TX_PIN - 8) * 4));
-    reg = GPIOD_AFH & ~(0xf << ((UART3_RX_PIN - 8) * 4));
-    GPIOD_AFH = reg | (UART3_PIN_AF << ((UART3_RX_PIN - 8) * 4));
+    reg = GPIO_MODE & ~ (0x03 << (UART_RX_PIN * 2));
+    GPIO_MODE = reg | (2 << (UART_RX_PIN * 2));
+    reg = GPIO_MODE & ~ (0x03 << (UART_TX_PIN * 2));
+    GPIO_MODE = reg | (2 << (UART_TX_PIN * 2));
+
+    reg = GPIO_AF & ~(0xf << (UART_TX_PIN * 4));
+    GPIO_AF = reg | (UART_PIN_AF << (UART_TX_PIN * 4));
+    reg = GPIO_AF & ~(0xf << (UART_RX_PIN * 4));
+    GPIO_AF = reg | (UART_PIN_AF << (UART_RX_PIN * 4));
 }
 
 int uart_tx(const uint8_t c)
 {
     uint32_t reg;
     do {
-        reg = UART3_SR;
+        reg = UART_SR;
     } while ((reg & UART_SR_TX_EMPTY) == 0);
-    UART3_DR = c;
+    UART_DR = c;
     return 1;
 }
 
 int uart_rx(uint8_t *c)
 {
-    volatile uint32_t reg = UART3_SR;
+    volatile uint32_t reg = UART_SR;
     if ((reg & UART_SR_RX_NOTEMPTY) != 0) {
-        reg = UART3_DR;
+        reg = UART_DR;
         *c = (uint8_t)(reg & 0xff);
         return 1;
     }
@@ -109,42 +139,42 @@ int uart_init(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
     /* Enable pins and configure for AF7 */
     uart_pins_setup();
     /* Turn on the device */
-    APB1_CLOCK_ER |= UART3_APB1_CLOCK_ER_VAL;
-    UART3_CR1 &= ~(UART_CR1_UART_ENABLE);
+    UART_CLOCK_ER |= UART_CLOCK_ER_VAL;
+    UART_CR1 &= ~(UART_CR1_UART_ENABLE);
 
     /* Configure for TX + RX */
-    UART3_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE);
+    UART_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE);
 
     /* Configure clock */
-    UART3_BRR =  CLOCK_SPEED / bitrate;
+    UART_BRR =  CLOCK_SPEED / bitrate;
 
     /* Configure data bits */
     if (data == 8)
-        UART3_CR1 &= ~UART_CR1_SYMBOL_LEN;
+        UART_CR1 &= ~UART_CR1_SYMBOL_LEN;
     else
-        UART3_CR1 |= UART_CR1_SYMBOL_LEN;
+        UART_CR1 |= UART_CR1_SYMBOL_LEN;
 
     /* Configure parity */
     switch (parity) {
         case 'O':
-            UART3_CR1 |= UART_CR1_PARITY_ODD;
+            UART_CR1 |= UART_CR1_PARITY_ODD;
             /* fall through to enable parity */
             /* FALL THROUGH */
         case 'E':
-            UART3_CR1 |= UART_CR1_PARITY_ENABLED;
+            UART_CR1 |= UART_CR1_PARITY_ENABLED;
             break;
         default:
-            UART3_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
+            UART_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
     }
     /* Set stop bits */
-    reg = UART3_CR2 & ~UART_CR2_STOPBITS;
+    reg = UART_CR2 & ~UART_CR2_STOPBITS;
     if (stop > 1)
-        UART3_CR2 = reg & (2 << 12);
+        UART_CR2 = reg & (2 << 12);
     else
-        UART3_CR2 = reg;
+        UART_CR2 = reg;
 
     /* Turn on uart */
-    UART3_CR1 |= UART_CR1_UART_ENABLE;
+    UART_CR1 |= UART_CR1_UART_ENABLE;
     return 0;
 }
 

From af09857f70770c4df717b5e29d4ea31acf7dbcc2 Mon Sep 17 00:00:00 2001
From: Alex Lanzano <lanzano.alex@gmail.com>
Date: Thu, 8 May 2025 16:37:51 -0400
Subject: [PATCH 3/7] Replace example stm32f4 config

This replaces the base stm32f4 config with more board specific examples
for the stm32f407 discovery kit and stm32f411 blackpill board.
---
 ...32f4.config => stm32f407-discovery.config} |  5 +++++
 config/examples/stm32f411-blackpill.config    | 21 +++++++++++++++++++
 2 files changed, 26 insertions(+)
 rename config/examples/{stm32f4.config => stm32f407-discovery.config} (76%)
 create mode 100644 config/examples/stm32f411-blackpill.config

diff --git a/config/examples/stm32f4.config b/config/examples/stm32f407-discovery.config
similarity index 76%
rename from config/examples/stm32f4.config
rename to config/examples/stm32f407-discovery.config
index d70b922996..d10b192b2f 100644
--- a/config/examples/stm32f4.config
+++ b/config/examples/stm32f407-discovery.config
@@ -9,3 +9,8 @@ WOLFBOOT_SECTOR_SIZE?=0x20000
 WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08020000
 WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08040000
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x08060000
+CLOCK_SPEED?=160000000
+STM32_PLLM?=8
+STM32_PLLN?=336
+STM32_PLLP?=2
+STM32_PLLQ?=7
diff --git a/config/examples/stm32f411-blackpill.config b/config/examples/stm32f411-blackpill.config
new file mode 100644
index 0000000000..3aaffa88d4
--- /dev/null
+++ b/config/examples/stm32f411-blackpill.config
@@ -0,0 +1,21 @@
+ARCH?=ARM
+TARGET?=stm32f4
+SIGN?=ED25519
+HASH?=SHA256
+VTOR?=1
+SPMATH?=1
+WOLFBOOT_ORIGIN?=0x08000000
+WOLFBOOT_PARTITION_SIZE?=0x20000
+WOLFBOOT_SECTOR_SIZE?=0x20000
+WOLFBOOT_PARTITION_BOOT_ADDRESS?=0x08020000
+WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x08040000
+WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x08060000
+CLOCK_SPEED?=84000000
+STM32_PLLM?=25
+STM32_PLLN?=336
+STM32_PLLP?=4
+STM32_PLLQ?=7
+USE_UART1?=1
+UART_FLASH?=1
+DEBUG?=1
+STM32?=1

From 72baf9644020c8b6c2267a9a5654a8519cacaad3 Mon Sep 17 00:00:00 2001
From: Alex Lanzano <lanzano.alex@gmail.com>
Date: Sat, 10 May 2025 18:00:13 -0400
Subject: [PATCH 4/7] Rename CPU_FREQ macro to CLOCK_SPEED. Remove CPU_FREQ
 from system.h

---
 test-app/app_stm32l0.c | 6 +++---
 test-app/system.h      | 2 --
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/test-app/app_stm32l0.c b/test-app/app_stm32l0.c
index 1697eb6141..9cf34a932f 100644
--- a/test-app/app_stm32l0.c
+++ b/test-app/app_stm32l0.c
@@ -81,8 +81,8 @@
 #define UART2_RX_PIN 2
 #define UART2_TX_PIN 3
 
-#ifndef CPU_FREQ
-#define CPU_FREQ (24000000)
+#ifndef CLOCK_SPEED
+#define CLOCK_SPEED (24000000)
 #endif
 
 static void uart2_pins_setup(void)
@@ -117,7 +117,7 @@ int uart_setup(uint32_t bitrate)
     UART2_CR1 &= (~UART_CR1_OVER8);
 
     /* Configure clock */
-    UART2_BRR |= (uint16_t)(CPU_FREQ / bitrate);
+    UART2_BRR |= (uint16_t)(CLOCK_SPEED / bitrate);
 
     /* Configure data bits to 8 */
     UART2_CR1 &= ~UART_CR1_SYMBOL_LEN;
diff --git a/test-app/system.h b/test-app/system.h
index e687623269..5cd9fcc2e2 100644
--- a/test-app/system.h
+++ b/test-app/system.h
@@ -23,8 +23,6 @@
 #ifndef SYSTEM_H_INCLUDED
 #define SYSTEM_H_INCLUDED
 
-/* System specific: PLL with 8 MHz external oscillator, CPU at 168MHz */
-#define CPU_FREQ (168000000)
 #define PLL_FULL_MASK (0x7F037FFF)
 
 /* Assembly helpers */

From 248fd985b3ccf56a28e3575e196001a41865801d Mon Sep 17 00:00:00 2001
From: Alex Lanzano <lanzano.alex@gmail.com>
Date: Fri, 16 May 2025 12:29:08 -0400
Subject: [PATCH 5/7] Update stm32f4 test-app to use config options to setup
 clock and uart

Allows the pll clock to be configured using the config macros instead of
being hard coded.
---
 test-app/app_stm32f4.c | 122 ++++++++++++++++++++++++++---------------
 test-app/system.c      |  18 ++++--
 2 files changed, 90 insertions(+), 50 deletions(-)

diff --git a/test-app/app_stm32f4.c b/test-app/app_stm32f4.c
index 7097f1ccb8..d105104df4 100644
--- a/test-app/app_stm32f4.c
+++ b/test-app/app_stm32f4.c
@@ -34,14 +34,15 @@
 
 #ifdef TARGET_stm32f4
 
-#define UART1 (0x40011000)
-
-#define UART1_SR       (*(volatile uint32_t *)(UART1))
-#define UART1_DR       (*(volatile uint32_t *)(UART1 + 0x04))
-#define UART1_BRR      (*(volatile uint32_t *)(UART1 + 0x08))
-#define UART1_CR1      (*(volatile uint32_t *)(UART1 + 0x0c))
-#define UART1_CR2      (*(volatile uint32_t *)(UART1 + 0x10))
+#ifndef CLOCK_SPEED
+#define CLOCK_SPEED (168000000)
+#endif
 
+/* Common UART Config */
+#if !defined(USE_UART1) && !defined(USE_UART3)
+#define USE_UART3
+#endif
+#define UART_PIN_AF 7
 #define UART_CR1_UART_ENABLE    (1 << 13)
 #define UART_CR1_SYMBOL_LEN     (1 << 12)
 #define UART_CR1_PARITY_ENABLED (1 << 10)
@@ -53,21 +54,52 @@
 #define UART_SR_RX_NOTEMPTY     (1 << 5)
 
 
-#define CLOCK_SPEED (168000000)
+/* Common GPIO Config */
+#define GPIO_MODE_AF (2)
 
-#define APB2_CLOCK_ER           (*(volatile uint32_t *)(0x40023844))
-#define UART1_APB2_CLOCK_ER (1 << 4)
+/* UART1 Config */
+#ifdef USE_UART1
+#define UART_RX_PIN 7
+#define UART_TX_PIN 6
 
-#define AHB1_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
-#define GPIOB_AHB1_CLOCK_ER (1 << 1)
+#define UART1 (0x40011000)
+#define UART_SR       (*(volatile uint32_t *)(UART1))
+#define UART_DR       (*(volatile uint32_t *)(UART1 + 0x04))
+#define UART_BRR      (*(volatile uint32_t *)(UART1 + 0x08))
+#define UART_CR1      (*(volatile uint32_t *)(UART1 + 0x0c))
+#define UART_CR2      (*(volatile uint32_t *)(UART1 + 0x10))
+
+#define UART_CLOCK_ER           (*(volatile uint32_t *)(0x40023844))
+#define UART_CLOCK_ER_VAL 	(1 << 4)
+
+#define GPIO_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
+#define GPIO_CLOCK_ER_VAL (1 << 1)
 #define GPIOB_BASE 0x40020400
+#define GPIO_MODE  (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
+#define GPIO_AF    (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
+#endif
 
-#define GPIOB_MODE  (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
-#define GPIOB_AFL   (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
-#define GPIOB_AFH   (*(volatile uint32_t *)(GPIOB_BASE + 0x24))
-#define UART1_PIN_AF 7
-#define UART1_RX_PIN 7
-#define UART1_TX_PIN 6
+/* UART3 Config */
+#ifdef USE_UART3
+#define UART_RX_PIN 9
+#define UART_TX_PIN 8
+
+#define UART3 (0x40004800)
+#define UART_SR       (*(volatile uint32_t *)(UART3))
+#define UART_DR       (*(volatile uint32_t *)(UART3 + 0x04))
+#define UART_BRR      (*(volatile uint32_t *)(UART3 + 0x08))
+#define UART_CR1      (*(volatile uint32_t *)(UART3 + 0x0c))
+#define UART_CR2      (*(volatile uint32_t *)(UART3 + 0x10))
+
+#define UART_CLOCK_ER           (*(volatile uint32_t *)(0x40023840))
+#define UART_CLOCK_ER_VAL 	    (1 << 18)
+
+#define GPIO_CLOCK_ER (*(volatile uint32_t *)(0x40023830))
+#define GPIO_CLOCK_ER_VAL (1 << 3)
+#define GPIOD_BASE 0x40020c00
+#define GPIO_MODE  (*(volatile uint32_t *)(GPIOD_BASE + 0x00))
+#define GPIO_AF    (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
+#endif
 
 #define MSGSIZE 16
 #define PAGESIZE (256)
@@ -100,26 +132,26 @@ void uart_write(const char c)
 {
     uint32_t reg;
     do {
-        reg = UART1_SR;
+        reg = UART_SR;
     } while ((reg & UART_SR_TX_EMPTY) == 0);
-    UART1_DR = c;
+    UART_DR = c;
 }
 
 static void uart_pins_setup(void)
 {
     uint32_t reg;
-    AHB1_CLOCK_ER |= GPIOB_AHB1_CLOCK_ER;
+    GPIO_CLOCK_ER |= GPIO_CLOCK_ER_VAL;
     /* Set mode = AF */
-    reg = GPIOB_MODE & ~ (0x03 << (UART1_RX_PIN * 2));
-    GPIOB_MODE = reg | (2 << (UART1_RX_PIN * 2));
-    reg = GPIOB_MODE & ~ (0x03 << (UART1_TX_PIN * 2));
-    GPIOB_MODE = reg | (2 << (UART1_TX_PIN * 2));
+    reg = GPIO_MODE & ~ (0x03 << (UART_RX_PIN * 2));
+    GPIO_MODE = reg | (2 << (UART_RX_PIN * 2));
+    reg = GPIO_MODE & ~ (0x03 << (UART_TX_PIN * 2));
+    GPIO_MODE = reg | (2 << (UART_TX_PIN * 2));
 
     /* Alternate function: use low pins (6 and 7) */
-    reg = GPIOB_AFL & ~(0xf << ((UART1_TX_PIN) * 4));
-    GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_TX_PIN) * 4));
-    reg = GPIOB_AFL & ~(0xf << ((UART1_RX_PIN) * 4));
-    GPIOB_AFL = reg | (UART1_PIN_AF << ((UART1_RX_PIN) * 4));
+    reg = GPIO_AF & ~(0xf << ((UART_TX_PIN) * 4));
+    GPIO_AF = reg | (UART_PIN_AF << ((UART_TX_PIN) * 4));
+    reg = GPIO_AF & ~(0xf << ((UART_RX_PIN) * 4));
+    GPIO_AF = reg | (UART_PIN_AF << ((UART_RX_PIN) * 4));
 }
 
 int uart_setup(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
@@ -128,40 +160,40 @@ int uart_setup(uint32_t bitrate, uint8_t data, char parity, uint8_t stop)
     /* Enable pins and configure for AF7 */
     uart_pins_setup();
     /* Turn on the device */
-    APB2_CLOCK_ER |= UART1_APB2_CLOCK_ER;
+    UART_CLOCK_ER |= UART_CLOCK_ER_VAL;
 
     /* Configure for TX + RX */
-    UART1_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE);
+    UART_CR1 |= (UART_CR1_TX_ENABLE | UART_CR1_RX_ENABLE);
 
     /* Configure clock */
-    UART1_BRR =  CLOCK_SPEED / bitrate;
+    UART_BRR =  CLOCK_SPEED / bitrate;
 
     /* Configure data bits */
     if (data == 8)
-        UART1_CR1 &= ~UART_CR1_SYMBOL_LEN;
+        UART_CR1 &= ~UART_CR1_SYMBOL_LEN;
     else
-        UART1_CR1 |= UART_CR1_SYMBOL_LEN;
+        UART_CR1 |= UART_CR1_SYMBOL_LEN;
 
     /* Configure parity */
     switch (parity) {
         case 'O':
-            UART1_CR1 |= UART_CR1_PARITY_ODD;
+            UART_CR1 |= UART_CR1_PARITY_ODD;
             /* fall through to enable parity */
         case 'E':
-            UART1_CR1 |= UART_CR1_PARITY_ENABLED;
+            UART_CR1 |= UART_CR1_PARITY_ENABLED;
             break;
         default:
-            UART1_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
+            UART_CR1 &= ~(UART_CR1_PARITY_ENABLED | UART_CR1_PARITY_ODD);
     }
     /* Set stop bits */
-    reg = UART1_CR2 & ~UART_CR2_STOPBITS;
+    reg = UART_CR2 & ~UART_CR2_STOPBITS;
     if (stop > 1)
-        UART1_CR2 = reg & (2 << 12);
+        UART_CR2 = reg & (2 << 12);
     else
-        UART1_CR2 = reg;
+        UART_CR2 = reg;
 
     /* Turn on uart */
-    UART1_CR1 |= UART_CR1_UART_ENABLE;
+    UART_CR1 |= UART_CR1_UART_ENABLE;
 
     return 0;
 }
@@ -171,9 +203,9 @@ char uart_read(void)
     char c;
     volatile uint32_t reg;
     do {
-        reg = UART1_SR;
+        reg = UART_SR;
     } while ((reg & UART_SR_RX_NOTEMPTY) == 0);
-    c = (char)(UART1_DR & 0xff);
+    c = (char)(UART_DR & 0xff);
     return c;
 }
 
@@ -215,7 +247,7 @@ void main(void) {
     flash_set_waitstates();
     clock_config();
     led_pwm_setup();
-    pwm_init(CPU_FREQ, 0);
+    pwm_init(CLOCK_SPEED, 0);
 
     /* Dim the led by altering the PWM duty-cicle
      * in isr_tim2 (timer.c)
@@ -224,7 +256,7 @@ void main(void) {
      * to the blue led increases/decreases making a pulse
      * effect.
      */
-    timer_init(CPU_FREQ, 1, 50);
+    timer_init(CLOCK_SPEED, 1, 50);
     uart_setup(115200, 8, 'N', 1);
     memset(page, 0xFF, PAGESIZE);
     asm volatile ("cpsie i");
diff --git a/test-app/system.c b/test-app/system.c
index a49b04f840..799bd2da91 100644
--- a/test-app/system.c
+++ b/test-app/system.c
@@ -57,12 +57,20 @@
 #define RCC_PRESCALER_DIV_4    9
 
 
-/* STM32F4-Discovery, 168 MHz */
+/* STM32F4 */
 #ifdef TARGET_stm32f4
-#  define PLLM 8
-#  define PLLN 336
-#  define PLLP 2
-#  define PLLQ 7
+#  if defined(STM32_PLLM) && defined(STM32_PLLN) && \
+    defined(STM32_PLLP) && defined(STM32_PLLQ)
+#    define PLLM STM32_PLLM
+#    define PLLN STM32_PLLN
+#    define PLLP STM32_PLLP
+#    define PLLQ STM32_PLLQ
+#  else
+#    define PLLM 8
+#    define PLLN 336
+#    define PLLP 2
+#    define PLLQ 7
+#  endif
 #  define PLLR 0
 #  define TARGET_FLASH_WAITSTATES 5
 #endif

From 5b36a6ddddf317d547d716928b4f626f2c425fbe Mon Sep 17 00:00:00 2001
From: Alex Lanzano <lanzano.alex@gmail.com>
Date: Sat, 21 Jun 2025 14:43:30 -0400
Subject: [PATCH 6/7] Fix build and test issues with stm32f4 targets

- Add the new CLOCK_SPEED and STM32_PLLx variables to the CMakeLists
  file

- Rename references of 'stm32f4.config' to 'stm32f407-discovery.config'
documentation and github workflow files.
---
 .github/workflows/footprint.yml               |  2 +-
 .github/workflows/test-build-cmake.yml        | 11 +++++++--
 .github/workflows/test-configs.yml            | 10 ++++++--
 CMakeLists.txt                                | 23 +++++++++++++++++++
 IDE/IAR/README.md                             |  4 ++--
 .../stm32f4-small-blocks-uart-update.config   |  5 ++++
 6 files changed, 48 insertions(+), 7 deletions(-)

diff --git a/.github/workflows/footprint.yml b/.github/workflows/footprint.yml
index 247403651d..9bd0dda681 100644
--- a/.github/workflows/footprint.yml
+++ b/.github/workflows/footprint.yml
@@ -30,7 +30,7 @@ jobs:
 
       - name: Select config
         run: |
-          cp config/examples/stm32f4.config .config && make include/target.h
+          cp config/examples/stm32f407-discovery.config .config && make include/target.h
 
       - name: Build key tools
         run: |
diff --git a/.github/workflows/test-build-cmake.yml b/.github/workflows/test-build-cmake.yml
index a322627b07..67b7f23f23 100644
--- a/.github/workflows/test-build-cmake.yml
+++ b/.github/workflows/test-build-cmake.yml
@@ -30,10 +30,17 @@ jobs:
       - name: Build wolfBoot
         run: make -C build
 
-      - name: Run CMake build for STM32F4
+      - name: Run CMake build for STM32F407-DISCOVERY
         run: |
           rm -rf ./build
-          cmake -B build -DWOLFBOOT_TARGET=stm32f4 -DWOLFBOOT_PARTITION_SIZE=0x20000 -DWOLFBOOT_SECTOR_SIZE=0x20000 -DWOLFBOOT_PARTITION_BOOT_ADDRESS=0x08020000 -DWOLFBOOT_PARTITION_UPDATE_ADDRESS=0x08040000 -DWOLFBOOT_PARTITION_SWAP_ADDRESS=0x08060000
+          cmake -B build -DWOLFBOOT_TARGET=stm32f4 -DWOLFBOOT_PARTITION_SIZE=0x20000 -DWOLFBOOT_SECTOR_SIZE=0x20000 -DWOLFBOOT_PARTITION_BOOT_ADDRESS=0x08020000 -DWOLFBOOT_PARTITION_UPDATE_ADDRESS=0x08040000 -DWOLFBOOT_PARTITION_SWAP_ADDRESS=0x08060000 -DCLOCK_SPEED=160000000 -DSTM32_PLLM=8 -DSTM32_PLLN=336 -DSTM32_PLLP=2 -DSTM32_PLLQ=7
+      - name: Build wolfBoot
+        run: make -C build
+
+      - name: Run CMake build for STM32F411-BLACKPILL
+        run: |
+          rm -rf ./build
+          cmake -B build -DWOLFBOOT_TARGET=stm32f4 -DWOLFBOOT_PARTITION_SIZE=0x20000 -DWOLFBOOT_SECTOR_SIZE=0x20000 -DWOLFBOOT_PARTITION_BOOT_ADDRESS=0x08020000 -DWOLFBOOT_PARTITION_UPDATE_ADDRESS=0x08040000 -DWOLFBOOT_PARTITION_SWAP_ADDRESS=0x08060000 -DCLOCK_SPEED=84000000 -DSTM32_PLLM=25 -DSTM32_PLLN=336 -DSTM32_PLLP=4 -DSTM32_PLLQ=7
       - name: Build wolfBoot
         run: make -C build
 
diff --git a/.github/workflows/test-configs.yml b/.github/workflows/test-configs.yml
index 87fa2f713c..a1167316fb 100644
--- a/.github/workflows/test-configs.yml
+++ b/.github/workflows/test-configs.yml
@@ -272,11 +272,17 @@ jobs:
       arch: arm
       config-file: ./config/examples/stm32f4-small-blocks-uart-update.config
 
-  stm32f4_test:
+  stm32f407_discovery_test:
     uses: ./.github/workflows/test-build.yml
     with:
       arch: arm
-      config-file: ./config/examples/stm32f4.config
+      config-file: ./config/examples/stm32f407-discovery.config
+
+  stm32f411_blackpill_test:
+    uses: ./.github/workflows/test-build.yml
+    with:
+      arch: arm
+      config-file: ./config/examples/stm32f411-blackpill.config
 
   stm32f7_dualbank_test:
     uses: ./.github/workflows/test-build.yml
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 4190bb990b..7708fba085 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -238,6 +238,29 @@ if(ARCH STREQUAL "ARM")
     if(${WOLFBOOT_TARGET} STREQUAL "stm32f4")
         set(ARCH_FLASH_OFFSET 0x08000000)
         set(WOLFBOOT_ORIGIN ${ARCH_FLASH_OFFSET})
+
+        if(NOT DEFINED CLOCK_SPEED)
+            message(FATAL_ERROR "CLOCK_SPEED must be defined")
+        endif()
+        if(NOT DEFINED STM32_PLLM)
+            message(FATAL_ERROR "STM32_PLLM must be defined")
+        endif()
+        if(NOT DEFINED STM32_PLLN)
+            message(FATAL_ERROR "STM32_PLLN must be defined")
+        endif()
+        if(NOT DEFINED STM32_PLLP)
+            message(FATAL_ERROR "STM32_PLLP must be defined")
+        endif()
+        if(NOT DEFINED STM32_PLLQ)
+            message(FATAL_ERROR "STM32_PLLQ must be defined")
+        endif()
+        add_compile_definitions(
+            CLOCK_SPEED=${CLOCK_SPEED}
+            STM32_PLLM=${STM32_PLLM}
+            STM32_PLLN=${STM32_PLLN}
+            STM32_PLLP=${STM32_PLLP}
+            STM32_PLLQ=${STM32_PLLQ}
+        )
     endif()
 
     if(${WOLFBOOT_TARGET} STREQUAL "stm32u5")
diff --git a/IDE/IAR/README.md b/IDE/IAR/README.md
index 587fb28a9e..05fa7b1c2c 100644
--- a/IDE/IAR/README.md
+++ b/IDE/IAR/README.md
@@ -12,7 +12,7 @@ application image starts at address 0x08020000.
 
 ```
 $template=Get-Content -path ..\..\include\target.h.in;
-Get-Content -path ..\..\config\examples\stm32f4.config | ForEach-Object {$v=$_.Split('?='); $a=$v[0]; $b=$v[2]; $template=($template -replace "##$a##",$b) };
+Get-Content -path ..\..\config\examples\stm32f407-discovery.config | ForEach-Object {$v=$_.Split('?='); $a=$v[0]; $b=$v[2]; $template=($template -replace "##$a##",$b) };
 $template=($template -replace "##.*##","");
 Set-Content -path target.h $template
 ```
@@ -91,4 +91,4 @@ If you are using a STM32F407-discovery board, a red LED will turn on upon applic
 
 ##  Armored Mode (Glitch Resistance)
 
-If you would like to enable the "Armored" mode (glitch resistance) in IAR you can set the compiler pre-processor macro `WOLFBOOT_ARMORED`. Note: This has only been tested with ECDSA on Cortex-M.
\ No newline at end of file
+If you would like to enable the "Armored" mode (glitch resistance) in IAR you can set the compiler pre-processor macro `WOLFBOOT_ARMORED`. Note: This has only been tested with ECDSA on Cortex-M.
diff --git a/config/examples/stm32f4-small-blocks-uart-update.config b/config/examples/stm32f4-small-blocks-uart-update.config
index 8b321c7e89..908bfc4629 100644
--- a/config/examples/stm32f4-small-blocks-uart-update.config
+++ b/config/examples/stm32f4-small-blocks-uart-update.config
@@ -27,3 +27,8 @@ WOLFBOOT_PARTITION_UPDATE_ADDRESS?=0x00000
 WOLFBOOT_PARTITION_SWAP_ADDRESS?=0x4000
 WOLFBOOT_LOAD_ADDRESS?=0x200000
 WOLFBOOT_LOAD_DTS_ADDRESS?=0x400000
+CLOCK_SPEED?=160000000
+STM32_PLLM?=8
+STM32_PLLN?=336
+STM32_PLLP?=2
+STM32_PLLQ?=7

From 1b37378a804d917ea7a74d0324f7d6f12262d6c6 Mon Sep 17 00:00:00 2001
From: Alex Lanzano <lanzano.alex@gmail.com>
Date: Sat, 21 Jun 2025 14:48:43 -0400
Subject: [PATCH 7/7] Fix shift overflow issue in stm32 uart driver

---
 hal/uart/uart_drv_stm32f4.c | 33 +++++++++++++++++++++++++++------
 1 file changed, 27 insertions(+), 6 deletions(-)

diff --git a/hal/uart/uart_drv_stm32f4.c b/hal/uart/uart_drv_stm32f4.c
index 4564371fba..758d0dcf91 100644
--- a/hal/uart/uart_drv_stm32f4.c
+++ b/hal/uart/uart_drv_stm32f4.c
@@ -70,7 +70,8 @@
 #define GPIO_CLOCK_ER_VAL (1 << 1)
 #define GPIOB_BASE 0x40020400
 #define GPIO_MODE  (*(volatile uint32_t *)(GPIOB_BASE + 0x00))
-#define GPIO_AF    (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
+#define GPIO_AFL    (*(volatile uint32_t *)(GPIOB_BASE + 0x20))
+#define GPIO_AFH    (*(volatile uint32_t *)(GPIOB_BASE + 0x24))
 #endif
 
 /* UART3 Config */
@@ -92,7 +93,8 @@
 #define GPIO_CLOCK_ER_VAL (1 << 3)
 #define GPIOD_BASE 0x40020c00
 #define GPIO_MODE  (*(volatile uint32_t *)(GPIOD_BASE + 0x00))
-#define GPIO_AF    (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
+#define GPIO_AFL   (*(volatile uint32_t *)(GPIOD_BASE + 0x20))
+#define GPIO_AFH   (*(volatile uint32_t *)(GPIOD_BASE + 0x24))
 #endif
 
 
@@ -106,10 +108,29 @@ static void uart_pins_setup(void)
     reg = GPIO_MODE & ~ (0x03 << (UART_TX_PIN * 2));
     GPIO_MODE = reg | (2 << (UART_TX_PIN * 2));
 
-    reg = GPIO_AF & ~(0xf << (UART_TX_PIN * 4));
-    GPIO_AF = reg | (UART_PIN_AF << (UART_TX_PIN * 4));
-    reg = GPIO_AF & ~(0xf << (UART_RX_PIN * 4));
-    GPIO_AF = reg | (UART_PIN_AF << (UART_RX_PIN * 4));
+    /* The alternate function register is split across two 32bit
+     * registers (AFL, AFH). AFL covers pins 0 through 7, and 
+     * AFH covers pins 8 through 15. The code below determines 
+     * which register to use at compile time based on the chosen
+     * pin number
+    */
+
+#if UART_TX_PIN > 7
+    reg = GPIO_AFH & ~(0xf << ((UART_TX_PIN - 8) * 4));
+    GPIO_AFH = reg | (UART_PIN_AF << ((UART_TX_PIN - 8) * 4));
+#else
+    reg = GPIO_AFL & ~(0xf << (UART_TX_PIN * 4));
+    GPIO_AFL = reg | (UART_PIN_AF << (UART_TX_PIN * 4));
+#endif
+
+#if UART_RX_PIN > 7
+    reg = GPIO_AFH & ~(0xf << ((UART_RX_PIN - 8) * 4));
+    GPIO_AFH = reg | (UART_PIN_AF << ((UART_RX_PIN - 8) * 4));
+#else
+    reg = GPIO_AFL & ~(0xf << (UART_RX_PIN * 4));
+    GPIO_AFL = reg | (UART_PIN_AF << (UART_RX_PIN * 4));
+#endif
+
 }
 
 int uart_tx(const uint8_t c)