transcript

# Reading D:/Modeltech_pe_edu_10.4a/tcl/vsim/pref.tcl
# do {cpu_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# 
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:30 on Dec 18,2015
# vlog -reportprogress 300 ipcore_dir/clk_ip.v 
# -- Compiling module clk_ip
# 
# Top level modules:
# 	clk_ip
# End time: 14:33:30 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:30 on Dec 18,2015
# vlog -reportprogress 300 regfile.v 
# -- Compiling module regfile
# 
# Top level modules:
# 	regfile
# End time: 14:33:30 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:30 on Dec 18,2015
# vlog -reportprogress 300 pc_module.v 
# -- Compiling module pc_module
# 
# Top level modules:
# 	pc_module
# End time: 14:33:30 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:30 on Dec 18,2015
# vlog -reportprogress 300 memory2writeback.v 
# -- Compiling module memory2writeback
# 
# Top level modules:
# 	memory2writeback
# End time: 14:33:30 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:30 on Dec 18,2015
# vlog -reportprogress 300 memory.v 
# -- Compiling module memory
# 
# Top level modules:
# 	memory
# End time: 14:33:30 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:30 on Dec 18,2015
# vlog -reportprogress 300 insFetch2insDecode.v 
# -- Compiling module insFetch2insDecode
# 
# Top level modules:
# 	insFetch2insDecode
# End time: 14:33:30 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:31 on Dec 18,2015
# vlog -reportprogress 300 insDecode2execute.v 
# -- Compiling module insDecode2execute
# 
# Top level modules:
# 	insDecode2execute
# End time: 14:33:31 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:31 on Dec 18,2015
# vlog -reportprogress 300 insDecode.v 
# -- Compiling module insDecode
# 
# Top level modules:
# 	insDecode
# End time: 14:33:31 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:31 on Dec 18,2015
# vlog -reportprogress 300 HILO.v 
# -- Compiling module hilo
# 
# Top level modules:
# 	hilo
# End time: 14:33:31 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:31 on Dec 18,2015
# vlog -reportprogress 300 execute2memory.v 
# -- Compiling module execute2memory
# 
# Top level modules:
# 	execute2memory
# End time: 14:33:31 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:31 on Dec 18,2015
# vlog -reportprogress 300 execute.v 
# -- Compiling module execute
# 
# Top level modules:
# 	execute
# End time: 14:33:31 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:31 on Dec 18,2015
# vlog -reportprogress 300 control.v 
# -- Compiling module control
# 
# Top level modules:
# 	control
# End time: 14:33:31 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:32 on Dec 18,2015
# vlog -reportprogress 300 vga.v 
# -- Compiling module vsync
# -- Compiling module hsync
# -- Compiling module vga
# 
# Top level modules:
# 	vga
# End time: 14:33:32 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:32 on Dec 18,2015
# vlog -reportprogress 300 ram.v 
# -- Compiling module ram
# 
# Top level modules:
# 	ram
# End time: 14:33:32 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:32 on Dec 18,2015
# vlog -reportprogress 300 mips.v 
# -- Compiling module mips
# 
# Top level modules:
# 	mips
# End time: 14:33:32 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:32 on Dec 18,2015
# vlog -reportprogress 300 ipcore_dir/instMem_ip.v 
# -- Compiling module instMem_ip
# 
# Top level modules:
# 	instMem_ip
# End time: 14:33:32 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:32 on Dec 18,2015
# vlog -reportprogress 300 btn.v 
# -- Compiling module btn_module
# 
# Top level modules:
# 	btn_module
# End time: 14:33:32 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:32 on Dec 18,2015
# vlog -reportprogress 300 cpu.v 
# -- Compiling module cpu
# 
# Top level modules:
# 	cpu
# End time: 14:33:32 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:32 on Dec 18,2015
# vlog -reportprogress 300 cpu_tb.v 
# -- Compiling module cpu_tb
# 
# Top level modules:
# 	cpu_tb
# End time: 14:33:33 on Dec 18,2015, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr  7 2015
# Start time: 14:33:33 on Dec 18,2015
# vlog -reportprogress 300 d:/Xilinx/14.7/ISE_DS/ISE/verilog/src/glbl.v 
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# End time: 14:33:33 on Dec 18,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# //  ModelSim PE Student Edition 10.4a Apr  7 2015 
# //
# //  Copyright 1991-2015 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //  THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL
# //  INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM
# //  DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552.
# //  FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER
# //  THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905.
# //
# // NOT FOR CORPORATE OR PRODUCTION USE.
# // THE ModelSim PE Student Edition IS NOT A SUPPORTED PRODUCT.
# // FOR HIGHER EDUCATION PURPOSES ONLY
# //
# vsim -gui -do "do {cpu_tb.fdo}" 
# Start time: 14:33:33 on Dec 18,2015
# Loading work.cpu_tb
# Loading work.cpu
# Loading work.clk_ip
# Loading unisims_ver.IBUFG
# Loading unisims_ver.DCM_SP
# Loading unisims_ver.dcm_sp_clock_divide_by_2
# Loading unisims_ver.dcm_sp_maximum_period_check
# Loading unisims_ver.dcm_sp_clock_lost
# Loading unisims_ver.BUFG
# Loading work.mips
# Loading work.pc_module
# Loading work.insFetch2insDecode
# Loading work.insDecode
# Loading work.insDecode2execute
# Loading work.execute
# Loading work.execute2memory
# Loading work.memory
# Loading work.memory2writeback
# Loading work.regfile
# Loading work.hilo
# Loading work.control
# Loading work.instMem_ip
# Loading xilinxcorelib_ver.DIST_MEM_GEN_V7_2
# Loading work.ram
# Loading work.vga
# Loading work.hsync
# Loading work.vsync
# Loading work.btn_module
# Loading work.glbl
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body.tree
# WARNING: This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation.
# ** Warning: (vsim-PLI-3408) Too few data words read on line 669 of file "instMem_ip.mif". Expected 2048, found 668.    : D:/Xilinx/14.7/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V7_2.v(248)
#    Time: 0 ps  Iteration: 0  Instance: /cpu_tb/uut/instMem/inst
add wave -position end  sim:/cpu_tb/uut/mips0/pc_module0/pc
add wave -position end  sim:/cpu_tb/uut/mips0/regfile0/regs
restart -f
run -all
# WARNING: This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation.
# ** Warning: (vsim-PLI-3408) Too few data words read on line 669 of file "instMem_ip.mif". Expected 2048, found 668.    : D:/Xilinx/14.7/ISE_DS/ISE/verilog/src/XilinxCoreLib/DIST_MEM_GEN_V7_2.v(248)
#    Time: 0 ps  Iteration: 0  Instance: /cpu_tb/uut/instMem/inst
# ** Note: $stop    : cpu_tb.v(116)
#    Time: 2321500 ns  Iteration: 0  Instance: /cpu_tb
# Break in Module cpu_tb at cpu_tb.v line 116
# End time: 14:38:11 on Dec 18,2015, Elapsed time: 0:04:38
# Errors: 0, Warnings: 2