-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathindex.html
More file actions
779 lines (699 loc) · 51.6 KB
/
index.html
File metadata and controls
779 lines (699 loc) · 51.6 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
<html>
<head>
<title>Zhufei Chu</title>
</head>
<head>
<style>
@keyframes flashing {
0% { opacity: 0; }
50% { opacity: 1; }
100% { opacity: 0; }
}
.red-star {
display: inline-block;
color: red;
font-size: 14px;
animation: flashing 1.5s infinite;
}
</style>
<style>
li {
line-height: 1.8;
}
#newsList li:nth-child(n+11) {
display: none;
}
#newsToggle {
font-size: 14px;
padding: 4px 12px;
margin-left: 10px;
cursor: pointer;
border: 1px solid #ccc;
border-radius: 4px;
background: #f8f8f8;
}
#newsToggle:hover {
background: #e8e8e8;
}
</style>
<script>
function toggleNews() {
const list = document.getElementById('newsList');
const items = list.getElementsByTagName('li');
const button = document.getElementById('newsToggle');
const isExpanded = list.classList.contains('expanded');
for (let i = 10; i < items.length; i++) {
items[i].style.display = isExpanded ? 'none' : 'list-item';
}
list.classList.toggle('expanded');
button.textContent = isExpanded ? 'More' : 'Less';
}
</script>
</head>
<!body background="images/background.jpg" BGCOLOR="#8C7853">
<body>
<base target="_top">
<table border=0 cellspacing=5>
<td width=143>
<img src="images/chu_2022.jpg" width=120>
</td>
<td width=800>
<h2>Zhufei Chu, Professor, Ningbo Univ.</h2>
<h4>
[<a href="#tools">Tools</a>]
[<a href="#tutorials">Tutorials</a>]
[<a href="#news">Recent News</a>]
[<a href="#about">About me</a>]
[<a href="#books">Books</a>]
[<a href="#publications">Publications</a>]
[<a href="#services">Professional Services</a>]
[<a href="#links">Links</a>]
[<a href="#address">Address</a>]
</h4>
<a href="mailto:chuzhufei@nbu.edu.cn">Email: <b>chuzhufei@nbu.edu.cn</b></a> <br>
Phone:(+86 574)8760-9496<br>
<br>
<strong>Research Interests:</strong><br>
Logic Synthesis, Physical Design, FPGA Synthesis, Emerging Nanotechnologies<br>
</td>
</td>
<td width=200>
</td>
<td>
<td width=350>
<img src="images/nbu.jpg" width=320>
</td>
</table>
<HR>
<h2> <a name="tools">Tools</a>
</h2>
<li>
<strong>ALSO</strong>: <strong>A</strong>dvanced <strong>L</strong>ogic
<strong>S</strong>ynthesis and <strong>O</strong>ptimization tool. <A HREF="https://github.com/nbulsi/also">[GitHub]</a>
<A HREF="https://gitee.com/zfchu/also">[Gitee]</a>. <span class="red-star">★</span> </li>
<li>stp: <strong>S</strong>emi-<strong>T</strong>ensor <strong>P</strong>roduct (STP) engine for Electronic Design Automation (EDA). <A HREF="https://github.com/nbulsi/stp">[GitHub]</a>
<A HREF="https://gitee.com/zfchu/stp">[Gitee]</a>. <span class="red-star">★</span> </li>
<h2> <a name="tutorials">Tutorials</a>
</h2>
<li>The <A HREF="https://www.eda2.com/iseda2024/tutorials.html">"Boolean Satisfiability Solving, State-of-the-Art"</a> Tutorial organized by Ningbo University, The Chinese University of Hong Kong, and Institute of Software, Chinese Academy of Sciences is presented at <A
HREF="https://www.eda2.com/conferenceHome/">ISEDA'24</a> on May 10th, 2024.
</li>
<li>The <A HREF="https://www.eda2.com/conferenceHome/program/detail?key=tutorial2">"Logic Synthesis Tools and Techniques: Insights from Academia and
Industry"</a> Tutorial organized by Ningbo University and Giga
Design Automation is presented at <A
HREF="https://www.eda2.com/conferenceHome/">ISEDA'23</a> on May 8th, 2023.
<a href="ISEDA2023.pdf" download >[handouts]</a>,
<a href="also.mp4" download >[demo video]</a>.
</li>
<li>An online tutorial <A
HREF="https://www.bilibili.com/video/BV1Ha411J7ow/?p=3">"Logic Synthesis,
Optimization, and Verification"</a> invited by Xidian University was
presented on Apr. 25th, 2022.</li>
<h2> <a name="news">Recent News</a> <button onclick="toggleNews()" id="newsToggle">More</button></h2>
<UL id="newsList">
<p class="big">
<li>Jan. 2026, Invited to serve as a Guest Editor of <A HREF="https://www.sciencedirect.com/special-issue/329310/2025-china-computer-federation-integrated-circuit-design-and-automation-conference-ccf-dac"> Integration, the VLSI Journal</a>.</li>
<li>July 2025, I will serve as the General Chair of <A
HREF="https://www.iwls.org/iwls2026/">IWLS'26</a> (Hong Kong, 2026).</li>
<li>July 2025, I will serve as the Organizing Chair of <A
HREF="https://conf.ccf.org.cn/ccfdac2025">CCFDAC'25</a> (Ningbo, Oct 2025).</li>
<li> July 2025, Invited to serve as a TPC member of <A
HREF="https://www.aspdac.com/">ASPDAC'26</a>.</li>
<li> June 2025, Invited to serve as a TPC member of <A
HREF="https://www.date-conference.com/">DATE'26</a>.</li>
<li> Feb. 2025, Invited to serve as a TPC member of <A
HREF="https://sasimi.jp/new/sasimi2025/">SASIMI'25</a>.</li>
<li> Jan. 2025, Invited to serve as TPC Chair of <A
HREF="http://iccs.org/index.html">ICCS'25</a>.</li>
<li> Jan. 2025, Invited to serve as a TPC
member of <A HREF="https://www.iwls.org/iwls2025/">IWLS'25</a>.</li>
<li>Dec. 2024, Invited to serve as High-Level, Behavioral, and Logic
Synthesis and Optimization Track
Chair of <A HREF="https://www.eda2.com/iseda/">ISEDA'25</a>.</li>
<li>Oct. 2024, Invited to serve as a TPC Member of <A
HREF="https://www.dac.com">
DAC'25</a>.</li>
<li> Sep. 2024, Jun as the first author won the ISEDA Honorable Mention
Paper Award at <A HREF="https://www.eda2.com/conferenceHome/">ISEDA'24</a>.</li>
<li> July 2024, Jiaxiang as the first author won the EDA Competition Winner
at <A HREF="https://smacd-conference.org/">SMACD'24</a>.</li>
<li>June 2024, Invited to serve as a TPC Member of <A
HREF="https://www.date-conference.com/tpc">
DATE'25</a>.</li>
<li>Mar. 2024, Invited to serve as a TPC Member of <A
HREF="https://std.samr.gov.cn/search/orgDetailView?data_id=EE1BA472BFC52880E05397BE0A0A248E">
National Standardization TC 599/ WG1</a>.</li>
<li>Oct. 2023, Invited to serve as a Research TPC Subcommittee Member of <A
HREF="https://www.dac.com/">
DAC'24</a>.</li>
<li>Oct. 2023, Invited to serve as Digital Design & Verification Track
Chair of <A HREF="https://www.eda2.com/conferenceHome/">ISEDA'24</a>.</li>
<li>Oct. 2023, Invited to serve as a <A
HREF=https://www.semiconchina.org/en/7>TPC member</a> and <A
HREF=https://www.semiconchina.org/en/1244>invited speaker</a> of
<A HREF=https://www.semiconchina.org/en/5>CSTIC'24</a>.</li>
<li>Aug. 2023, Invited to serve as a Competition Committee Member of <A HREF="https://eda.icisc.cn/activity/toTpcType">EDA Elite Challenge</a>.</li>
<li> July 2023, Chengyu as the first author won the Honorable Paper Award
at <A HREF="https://www.eda2.com/conferenceHome/">ISEDA'23</a>.</li>
<li> May 2023, Invited to serve as Publication Chair of <A HREF="https://conf.ccf.org.cn/ccfdac23">CCFDAC'23</a>.</li>
<li> Mar. 2023, Invited to serve as a Editorial Board Member of <A
HREF="https://jeit.ac.cn/news/About%20Journal.htm">JEIT</a>.</li>
<li> Mar. 2023, Invited to serve as TPC Chair of <A
HREF="http://iccs.org/index.html">ICCS'23</a>.</li>
<li> Dec. 2022, Promoted to be a Full Professor.</li>
<li> Dec. 2022, Invited to serve as Finance Chair and TPC
member of <A HREF="https://www.iwls.org/iwls2023/">IWLS'23</a>.</li>
<li>Nov. 2022, Invited to serve as a Research TPC Subcommittee Member of <A
HREF="https://www.dac.com/">
DAC'23</a>.</li>
<li>Oct. 2022, Invited to serve as Digital Design & Verification Track
Chair of <A HREF="https://www.eda2.com/conferenceHome/">ISEDA'23</a>.</li>
<li> May 2022, Invited to serve as sub-forum co-chair and a TPC member of <A
HREF="http://conf.ccf.org.cn/chip2022">CCF
Chip'22</a>.</li>
<li> Oct. 2021, Invited to serve as a TPC member of <A
HREF="https://embeddedandvlsidesignconference.org/">VLSID'22</a>.</li>
<li> Oct. 2021, Won the Best Paper Award at <A HREF="http://conf.ccf.org.cn/ccfdac2021">CCFDAC'21</a>. (<A HREF="https://news.nbu.edu.cn/info/1004/42169.htm">NBU link</a>)</li>
<li> Aug. 2021, Invited to serve as Finance Chair and a TPC
member of <A HREF="https://www.iwls.org/iwsl2022/">IWLS'22</a>.</li>
<li> Jan. 2021, Invited to serve as Proceedings Chair and a TPC member of <A HREF="https://www.iwls.org/iwls2021/">IWLS'21</a>.</li>
<li> Oct. 2020, Invited to serve as a TPC member of <A
HREF="https://embeddedandvlsidesignconference.org/">VLSID'21</a>.</li>
<li> Aug. 2020, Invited to serve as a TPC member of <A
HREF="https://www.semiconchina.org/en/7">
CSTIC'21</a> (Symposium IX). </li>
<li> Aug. 2020, Invited to serve as a TPC member of <A
HREF="https://sites.google.com/view/vlsi-soc-2020/home">
VLSI-SoC'20</a> (PhD Forum). </li>
<li> Aug. 2020, Invited to serve as a TPC member of <A
HREF="http://www.iccd-conf.com/Home.html">
ICCD'20</a> (Special Sessions). </li>
<li> Mar. 2020, Invited to serve as a TPC member of <A
HREF="https://conf.ccf.org.cn/web/html5/index.html?globalId=574c0f1ef8c04db9bd3b5d718e091b5c&type=1"> CCFDAC'20</a>. </li>
<li> Feb. 2020, Invited to serve as a TPC member of <A
HREF="https://coinsconf.com/"> COINS'20</a>. </li>
<li> Jan. 2020, Invited to serve as Proceedings Chair of <A
HREF="http://www.iwls.org/iwls2020/"> IWLS'20</a>. </li>
<li> June 2019, Invited to serve as a TPC member of <A
HREF="https://embeddedandvlsidesignconference.org/">VLSID'20</a>.</li>
<li> Feb. 2019, Invited to serve as Proceedings Chair and
Session Chair of <A HREF="http://www.iwls.org/iwls2019/"> IWLS'19</a>. </li>
</UL>
<HR>
<h2> <a name="about">About me</a> </h2>
<UL>
<p class="big">
<strong>Zhufei Chu</strong> <A
HREF="https://zhaosheng.eol.cn/11646/tutors/index/daoshidetail?school_id=461&m_id=35619&ds_id=19760">[NBU
link]</a>, born on Oct. 24th, 1986, received his B.S. degree in electronic engineering from Shandong University, Weihai, China, in 2008, and his M.S. and Ph.D. degrees in communication and information systems from Ningbo University, Ningbo, in 2011 and 2014, respectively.
He was a postdoctoral fellow at the Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, from 2016 to 2017, in the group of <A HREF="http://si2.epfl.ch/~demichel/">Prof. Giovanni De Micheli</a>.
He is currently a full professor at Ningbo University, Ningbo.
His current research interests focus on various aspects of logic synthesis and its applications.
</UL>
<HR>
<h2> <a name="books">Books</a> </h2>
Kaihui Tu, Xifan Tang, Cunxi Yu, Lana Josipovic, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>,
<strong><A
HREF="https://link.springer.com/book/10.1007/978-981-99-7755-0">FPGA
EDA : Design Principles and Implementation</strong></a>, Springer, Jan. 2024.
<h2> <a name="publications">Publications <a href="https://scholar.google.com/citations?hl=en&user=0spez40AAAAJ&view_op=list_works&gmla=AJsN-F7L0_K-NorY6eoZe8Pw5s7fVCiAq78gP2ooH9ToyokXmHtZMdOpLqZcA1SdxYMErXBK7c3ojrJANocYOruEoCCtFhL_X66ox6BQu7pD55qOLBSKisIgW6UyODbwLeEAWXk-sftYo8WCNcAkyazMLZ_JKn6yQ"> [Google Scholar]</a> <a href="http://dblp.uni-trier.de/pers/hd/c/Chu:Zhufei"> [DBLP]
<a href="https://orcid.org/0000-0001-5718-4822" target="orcid.widget" rel="noopener noreferrer"
style="vertical-align:top;"><img
src="https://orcid.org/sites/default/files/images/orcid_16x16.png"
style="width:1em;margin-right:.5em;" alt="ORCID iD icon">[orcid]</a>
</a></a> </h2>
<p>
<OL>
<h3> 2026 </h3>
<li>
Jiaxiang Pan, Yinshui Xia, Lunyao Wang, and <A HREF="https://zfchu.github.io">Zhufei Chu</a>, "<A HREF="https://ieeexplore.ieee.org/document/11340701">LV-MAGIC: Logic Synthesis and Verification for MAGIC based In-Memory Computing</a>", <i> IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
</i>, <strong>TCAD</strong>, Early Access, doi: 10.1109/TCAD.2026.3652093.
</li>
<li>Qiyao He, Zhang Hu, Yinshui Xia, Lunyao Wang, and <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, "<A HREF="https://www.sciencedirect.com/science/article/abs/pii/S0167926025002378">Enhancing Logic Optimization of Alliance Tool based on Directed Acyclic Graphs</a> ", <i>Integration, the VLSI Journal </i>, Volume 106, January 2026, 102580. </li>
<li> Lingfeng Zhou, Yilong Zhou, Hao Gong, Zhengyuan Shi, Qiang Xu, <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yue Wu, and Xiaoyan
Yang, "DeepCut: Structure-Aware GNN Framework for Efficient Cut Timing
Prediction in Logic Synthesis", <strong> ASPDAC'26</strong>,
<i>Asia and South Pacific Design Automation Conference</i>, Hongkong, China, Jan. 2026.</li>
<h3> 2025 </h3>
<p class="big">
<li>Hongyang Pan, Sen Liu, Yong Xiao, Yun Shao, Keren Zhu, Fan Yang, Xuan Zeng and <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, "<A HREF="https://dl.acm.org/doi/full/10.1145/3749103">Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis</a>", <i>ACM Transactions on Design Automation of Electronic Systems
</i>, <strong>TODAES</strong>, August 2025, 30(5): 77:1-77:29.</li>
<li>Tingting Liu and <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, "<A HREF="https://www.sciencedirect.com/science/article/abs/pii/S1879239125000025">Implication logic synthesis and optimization methods for memristor-based logic circuits</a>", <i>Microelectronics Journal</i>, March 2025, 157: 106553.</li>
<li> Zhengyuan Shi, Chengyu Ma, Ziyang Zheng, Lingfeng Zhou, Hongyang Pan, Wentao Jiang, Fan Yang, Xiaoyan Yang, <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, and Qiang Xu, "DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning", <strong> ICCAD' 25</strong>,
<i>International Conference on Computer-Aided Design</i>, Munich, Germany, Oct. 2025.</li>
<li>
Zhengyuan Shi, Wentao Jiang, Xindi Zhang, Jin Luo, Yun Liang, <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, and Qiang Xu, "<A HREF="https://drops.dagstuhl.de/storage/00lipics/lipics-vol340-cp2025/LIPIcs.CP.2025.34/LIPIcs.CP.2025.34.pdf">DynamicSAT: Dynamic Configuration Tuning for SAT Solving</a>", <strong> CP' 25</strong>,
<i>The 31st International Conference on Principles and Practice of Constraint Programming</i>, Glasgow, Scotland, Aug. 2025.
</li>
<li>
Zeju Li, Changran Xu, Zhengyuan Shi, Zedong Peng, Yi Liu, Yunhao Zhou, Lingfeng Zhou, Chengyu Ma, Jianyuan Zhong, Xi Wang, Jieru Zhao, <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, Xiaoyan Yang, and Qiang Xu, "<A HREF="https://ieeexplore.ieee.org/document/11105939">DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis</a>", <strong> LAD' 25</strong>, <i>IEEE International Conference on LLM-Aided Design</i>, Stanford, CA, USA, June 2025.
</li>
<li>
Jiaxin Peng, Zhang Hu, Yinshui Xia, Lunyao Wang, and <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>,"<A HREF="https://ieeexplore.ieee.org/document/11100963">SAT-Sweeping Based on XOR-Majority Graph</a>", <strong> ISEDA' 25</strong>, <i>IEEE International Symposium of EDA</i>, May 2025, Hong Kong, China.
</li>
<li>
Chengkai Qiu, Yanzhen Wang, Hongyang Pan, Yinshui Xia, Lunyao Wang, and <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>,"<A HREF="https://ieeexplore.ieee.org/document/11100908">STPSim: Accelerating Circuit Simulation via Semi-Tensor Product-Based Parallelism</a>", <strong> ISEDA' 25</strong>, <i>IEEE International Symposium of EDA</i>, May 2025, Hong Kong, China.
</li>
<li>
Haonan Wei, Wentao Jiang, Zhang Hu, Zhengyuan Shi, Yinshui Xia, Lunyao Wang, and <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>,"<A HREF="https://ieeexplore.ieee.org/document/11100798">Auto-CEC: Combinational Equivalence Checking via Intelligent Sweeping Engine Selection</a>", <strong> ISEDA' 25</strong>, <i>IEEE International Symposium of EDA</i>, May 2025, Hong Kong, China.
</li>
<li>
Chen Lv, Chengyu Ma, Hongyang Pan, Yinshui Xia, Lunyao Wang, and <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>,"<A HREF="https://ieeexplore.ieee.org/document/11101222">Area-oriented Boolean Resubstitution with Efficient Dependency Function Computation</a>", <strong> ISEDA' 25</strong>, <i>IEEE International Symposium of EDA</i>, May 2025, Hong Kong, China.
</li>
<li>
Zhang Hu, Hongyang Pan, Yinshui Xia, Lunyao Wang and <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, "<A HREF="https://ieeexplore.ieee.org/document/11133368">Mixed Structural Choice Operator: Enhancing Technology Mapping with Heterogeneous Representations</a>", <strong> DAC' 25</strong>, <i>ACM/IEEE Design Automation Conference</i>, San Francisco, USA, June 2025.
</li>
<li>
Zhengyuan Shi, Tiebing Tang, Jiaying Zhu, Sadaf Khan, Hui-Ling Zhen, Mingxuan Yuan, <A
HREF="https://zfchu.github.io/">Zhufei Chu</a> and Qiang Xu, "<A HREF="https://ieeexplore.ieee.org/document/11133310">Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT Solving</a>", <strong> DAC' 25</strong>, <i>ACM/IEEE Design Automation Conference</i>, San Francisco, USA, June 2025.
</li>
<li>
Liwei Ni, Rui Wang, Miao Liu, Xingyu Meng, Xiaoze Lin, Junfeng Liu,
Guojie Luo, <A HREF="https://zfchu.github.io">Zhufei Chu</a>, Weikang Qian, Xiaoyan Yang, Biwei Xie, Xingquan
Li, Huawei Li, "<A HREF="https://ieeexplore.ieee.org/document/10943238">OpenLS-DGF: An Adaptive Open-Source Dataset Generation
Framework for Machine Learning Tasks in Logic Synthesis</a>", <i> IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
</i>, <strong>TCAD</strong>, Oct. 2025, 44(10):3830-3843.
</li>
<li>
Hongyang Pan, Keren Zhu, Fan Yang, <A
HREF="https://zfchu.github.io/">Zhufei Chu</a> and Xuan Zeng,
"<A HREF="https://ieeexplore.ieee.org/document/10993190">ELMap: Area-Driven LUT Mapping with k-LUT Network Exact Synthesis</a>",
<strong> DATE'25</strong>, <i>2025 Design, Automation
and Test in Europe Conference</i>, Lyon, France, Mar. 2025.
</li>
<li>
Qiyao He and <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>,"<A HREF="https://ieeexplore.ieee.org/document/11017876">Enhancing Alliance VLSI Toolchain by Mixed Gate-level Logic Synthesis</a>", <strong>CSTIC' 25</strong>, <i>2025 Conference of Science and Technology for Integrated Circuits</i>, Shanghai, China, Mar. 2025.
</li>
<h4> 2024 </h3>
<p class="big">
<li>
Lei Chen, Yiqi Chen, <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li,
Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue,
Evangeline F.Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, and Sunan Zou,
"<A HREF="https://link.springer.com/article/10.1007/s11432-024-4155-7"> Large
Circuit Models: Opportunities and Challenges </a>", <i>Science China Information Sciences</i>, Sep. 2024, 67(10): 200402.
</li>
<li>Jiaxiang Pan and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, "
<A HREF="https://ieeexplore.ieee.org/document/10745461">Area-Aware Logic Mapping for MAGIC based In-Memory Computing</a>", <strong>SMACD' 24</strong>, <i>International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design</i>, July
2024, Volos, Greece. (<strong>EDA Competition Winner</strong>) <span class="red-star">★</span> </li>
<li>Qiyu Yang, Zheng-Dong Luo, Fei Xiao, Junpeng Zhang, Dawei Zhang,
Dongxin Tan, Xuetao Gan, Yan Liu, <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yinshui Xia, and Genquan Han,
"<A HREF="https://link.springer.com/article/10.1007/s11432-024-4004-9#citeas">Solid-state nonvolatile memories based on vdW heterostructure-based vertical-transport ferroelectric field-effect transistors</a>",
<i>Science China Information Sciences</i>, 67, 160405 (2024).
</li>
<li>
Lei Chen, Yiqi Chen, <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li,
Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue,
Evangeline F.Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, and Sunan Zou,
"<A HREF="https://arxiv.org/abs/2403.07257">The Dawn of AI-Native EDA: Promises and Challenges of Large
Circuit Models</a>", arXiv preprint arXiv:2403.07257, Mar. 2024.
</li>
<li>
朱柏成,<A HREF="https://zfchu.github.io/">储著飞</a>,潘鸿洋,王伦耀,夏银水,<A HREF="https://www.jcad.cn/cn/article/doi/10.3724/SP.J.1089.2024.19949">基于XMG的乘法器电路等价性验证算法</a>,<i>计算机辅助设计与图形学学报</i>,2024, 36(3): 443-451.
</li>
<li>
赵子豪,<A HREF="https://zfchu.github.io/">储著飞</a>, 王伦耀,夏银水,<A HREF="https://www.jcad.cn/cn/article/doi/10.3724/SP.J.1089.2024.19951">多级混合极性Reed-Muller逻辑电路功耗优化</a>,<i>计算机辅助设计与图形学学报</i>,2024, 36(4): 615-624.
</li>
<li> Ming Yan, Guanghai Dong, Yong Xiao, Yun Shao, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, "
<A HREF="https://ieeexplore.ieee.org/document/10618072">Exact Synthesis and Inversion Optimization for RM3 based Logic-in-Memory</a>", <strong>ISEDA' 24</strong>, <i> IEEE International Symposium of EDA</i>, May 2024, pp. 266-271, Xi'an, China.</li>
<li> Zhang Hu, Chengyu Ma, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, "
<A HREF="https://ieeexplore.ieee.org/document/10617691">A Novel Structural Choices Generation Method for Logic Restructuring</a>", <strong>ISEDA' 24</strong>, <i> IEEE International Symposium of EDA</i>, May 2024, pp. 306-311, Xi'an, China.</li>
<li> Jun Zhu, Hongyang Pan, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, "
<A HREF="https://ieeexplore.ieee.org/document/10617946">Multiplication Complexity Optimization based on Quantified Boolean Formulas</a>", <strong>ISEDA' 24</strong>, <i> IEEE International Symposium of EDA</i>, May 2024, pp. 332-336, Xi'an, China. (<strong>Honorable Mention Paper Award</strong>) <span class="red-star">★</span> </li>
<li> Yuting Cai, Yue Wu, Xiaoyan Yang, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, "
<A HREF="https://ieeexplore.ieee.org/document/10618015">A Logic Optimization Method Using Reinforcement Learning</a>", <strong>ISEDA' 24</strong>, <i> IEEE International Symposium of EDA</i>, May 2024, pp. 312-317, Xi'an, China.</li>
<li>
<A HREF="https://zfchu.github.io/">储著飞</a>, 马铖昱, 闫鸣, 潘家祥,
潘鸿洋, 王伦耀, 夏银水,"<A
HREF="https://jeit.ac.cn/cn/article/doi/10.11999/JEIT231457">基于半张量积的逻辑综合研究进展</a>",<i>电子与信息学报</i>,2024, 46(09):3490-3502.
</li>
<li>
Huali Duan, Erping Li, Qinyi Huang, Da Li, <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Jian Wang, and Wenchao Chen,
"<A HREF="https://pubs.aip.org/aip/jap/article/135/10/104502/3270993">Investigation of thermal stress effects on subthreshold conduction in nanoscale p-FinFET from Multiphysics perspective</a>".
<i>Journal of Applied Physics</i>, Mar. 2024, 135(10).
</li>
<li> Tiancheng Li, Erping Li, Huali Duan, <A
HREF="https://zfchu.github.io">Zhufei Chu</a>, Jian Wang, and Wenchao Chen,
"Artificial neural network models for
metal-ferroelectric-insulator-semiconductor ferroelectric tunnel junction memristor",
<i>Microelectronics Journal</i>, Feb. 2024, Vol 144, 106083.</li>
<li>
Hongyang Pan, Yinshui Xia, Lunyao Wang, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>,
"<A HREF="https://ieeexplore.ieee.org/document/10330666">Semi-Tensor
Product Based Exact Synthesis for Logic Rewriting</a>", <i> IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
</i>, <strong>TCAD</strong>, Apr. 2024, 43(4):1093-1106.
</li>
<li>
Hongyang Pan, Ruibing Zhang, Yinshui Xia, Lunyao Wang, Fan Yang, Xuan
Zeng, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>,
"<A HREF="https://ieeexplore.ieee.org/document/10546678">A Semi-Tensor Product based Circuit Simulation for SAT-sweeping</a>", <strong> DATE' 24</strong>, <i>2024 Design, Automation
and Test in Europe Conference</i>, Valencia, Spain, Mar. 2024.
</li>
<li>
Sen Liu, Hongwei Zhou, Yinshui Xia, Lunyao Wang and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, ""<A HREF="https://ieeexplore.ieee.org/document/10532048">Logic Synthesis for XOR-AND Graphs via Reed-Muller Representations</a>," <strong> CSTIC' 24</strong>, <i>2024 Conference of Science and Technology for Integrated Circuits</i>, Shanghai, China, Mar. 2024.
</li>
<h3> 2023 </h3>
<p class="big">
<li>Kunmei Hu and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>,
"<A HREF=https://www.sciencedirect.com/science/article/pii/S002626922300318X>An
Efficient Circuit-based SAT Solver and Its Application in Logic
Equivalence Checking</a>", <i>Microelectronics Journal</i>, Vol 142, 106005, Dec. 2023. </li>
<li>Zhengyuan Shi, Hongyang Pan, Sadaf Khan, Min Li, Yi Liu, Junhua
Huang, Hui-Ling Zhen, Mingxuan Yuan, <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, Qiang Xu,"<A HREF="https://ieeexplore.ieee.org/document/10323798">DeepGate2:
Functionality-Aware Circuit Representation
Learning</a>",<strong>ICCAD'23</strong>, 2023 International Conference on Computer-Aided Design, San
Francisco, CA, USA, Nov. 2023.</li>
<li>Hongyang Pan and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, "<A
HREF="https://jcst.ict.ac.cn/EN/10.1007/s11390-022-1981-4">A
Semi-Tensor Product Based All Solutions Boolean Satisfiability Solver</a>",<i>Journal of Computer Science and
Technology (<strong>JCST</strong>)</i>, 38(3):702-713, May 2023. </li>
<li>
Hongyang Pan and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, "<A
HREF="https://ieeexplore.ieee.org/document/10137287">Exact Synthesis based on Semi-Tensor Product
Circuit Solver</a>", <strong> DATE' 23</strong>, <i>2023 Design, Automation
and Test in Europe Conference</i>, Antwerp, Belgium, Apr. 2023.
</li>
<li> Hongyang Pan, Ruibing Zhang, Yinshui Xia, Lunyao Wang, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, "Semi-Tensor Product based Circuit Simulation for SAT sweeping
", <strong>IWLS' 23</strong>, <i> International Workshop on Logic & Synthesis</i>, June
2023, Lausanne, Switzerland.</li>
<li> Sen Liu, Hongyang Pan, Yinshui Xia, Lunyao Wang, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, "Multiplicative Complexity Optimization Based on Boolean-Difference Resubstitution", <strong>IWLS' 23</strong>, <i> International Workshop on Logic & Synthesis</i>, June
2023, Lausanne, Switzerland.</li>
<li> <A HREF="https://zfchu.github.io/">储著飞</a>、洪庆辉、李冰、刘成、尹勋钊、岳金山、张吉良、卓成、李华伟,"<A
HREF="https://dl.ccf.org.cn/article/detail.html?_ack=1&id=6476820625082368">存内计算研究进展与发展趋势</a>",<i>2021-2022中国计算机科学技术发展报告(纸质版)</i>, 2023年5月, pp. 195-252. </li>
<li> 张健、蔡少伟、陈振邦、贺飞、李占山、马菲菲、吴志林、钟卓炜、<A HREF="https://zfchu.github.io/">储著飞</a>,"<A
HREF="https://dl.ccf.org.cn/article/detail.html?_ack=1&id=6476813273516032">约束求解技术与应用</a>",<i>2021-2022中国计算机科学技术发展报告(电子版)</i>, 2023年5月, pp. 1-47. </li>
<li> Chunliu Liao, Yong Xiao, Yun Shao, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, "<A HREF="https://ieeexplore.ieee.org/document/10218548">
Improved Depth-Aware Circuit Partitioning for Mixed Logic Synthesis</a>", <strong>ISEDA' 23</strong>, <i> IEEE International Symposium of EDA</i>, May
2023, pp.170-173, Nanjing, China.</li>
<li> Chengyu Ma, Yong Xiao, Yun Shao, and <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, "<A HREF="https://ieeexplore.ieee.org/document/10218518">An Integrated Logic
Function Decomposition Flow for XOR-Majority Graphs</a>", <strong>ISEDA'23</strong>, <i> IEEE International Symposium of EDA</i>, May 2023, pp. 146-149,
Nanjing, China. (<strong>Honorable Paper Award</strong>) <span class="red-star">★</span> </li>
<li>
<A HREF="https://zfchu.github.io/">储著飞</a>,潘鸿洋,"<A
HREF="https://jeit.ac.cn/cn/article/doi/10.11999/JEIT220391">基于布尔可满足性的精确逻辑综合综述</a>",<i>电子与信息学报</i>,2023,
45(1):14-23. (<strong>Invited</strong>)
</li>
<li> Ruibing Zhang, Hongyang Pan, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, "<A HREF="https://ieeexplore.ieee.org/document/10219157">Logic Circuit Simulation based on Semi-Tensor Product</a>",
<strong>CSTIC' 23</strong>, <i> China Semiconductor Technology International Conference</i>, June
2023, Shanghai, China.</li>
<li> Kunmei Hu and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, "<A HREF="https://ieeexplore.ieee.org/document/10219398">
CirSAT: An Efficient Circuit-based SAT Solver via Fanout-driven Decision Heuristic</a>", <strong>CSTIC' 23</strong>, <i> China Semiconductor Technology International Conference</i>, June
2023, Shanghai, China.</li>
<h3> 2022 </h3>
<p class="big">
<li>
<A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Chuanhe Shang, Tingting
Zhang, Yinshui Xia, Lunyao Wang, and Weiqiang Liu, "<A
HREF="https://ieeexplore.ieee.org/document/9916208">Efficient Design of
Majority-Logic-Based Approximate Arithmetic Circuits</a>", <i>IEEE Transactions
on Very Large Scale Integration Systems</i> (<strong>TVLSI</strong>), Dec.
2022, 30(12):1827-1839.
</li>
<li>
Qing Wan, Changjin Wan, Huaqiang Wu, Yuchao Yang, Xiaohe Huang, Peng Zhou, Lin Chen, Tian-Yu Wang, Yi Li, Kanhao Xue, Yuhui He, Xiangshui Miao, Xi Li, Chenchen Xie, Houpeng Chen, Zhitang Song, Hong Wang, Yue Hao, Junyao Zhang, Jia Huang, Zheng Yu Ren, Li Qiang Zhu, Jianyu Du, Chen Ge, Yang Liu, Guanglong Ding, Ye Zhou, Su-Ting Han, Guosheng Wang, Xiao Yu, Bing Chen, <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Lunyao Wang, Yinshui Xia, Chen Mu, Feng Lin, Chixiao Chen, Bojun Cheng, Yannan Xing, Weitao Zeng, Hong Chen, Lei Yu, Giacomo Indiveri and Ning Qiao, "<A HREF="http://iopscience.iop.org/article/10.1088/2634-4386/ac7a5a">2022 roadmap on neuromorphic devices & applications research in China </a>" (Section 12: Automated synthesis and mapping), <i>Neuromorphic Computing and Engineering</i>, 2022, 2(4): 042501. (<strong>Invited</strong>)
</li>
<li> Chenghao Yang, Yinshui Xia, <A HREF="https://zfchu.github.io/">Zhufei
Chu</a>, and Xiaojing Zha "<A HREF="https://ieeexplore.ieee.org/abstract/document/9759467/">Logic Synthesis Optimization Sequence tuning using RL-based LSTM and Graph Isomorphism Network</a>",
<i>IEEE Transactions on Circuits and Systems II: Express Briefs
(<strong>TCAS-II</strong>)</i>, Aug. 2022, 69(8):3600-3604.</li>
<li> Peng Liu, Jianguo Ni, and <A HREF="https://zfchu.github.io/">Zhufei
Chu</a>, "<A HREF="https://link.springer.com/article/10.1007/s10773-022-05000-5">Wire-crossings Optimization
Based on Majority-of-five and XOR-of-three Primitives in QCA </a>",
<i>International Journal of Theoretical Physics</i>, Mar. 2022, 61(3): 1-22.</li>
<li>Xiang He and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>,
"<A HREF="https://www.sciencedirect.com/science/article/pii/S0167926021001243">Stochastic Circuit Synthesis via Satisfiability</a>", <i> Integration, the
VLSI Journal</i>, May 2022, 84:84-91. </li>
<li>Hongwei Zhou, Yong Xiao, Yun Shao, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>,
"<A HREF="https://ieeexplore.ieee.org/document/9856871/">Area-aware optimization of XOR-AND Graph based on Reed-Muller logic expansion</a>",
<strong>CSTIC' 22</strong>, <i> China Semiconductor Technology International Conference</i>, Mar
2022, Hangzhou, China. </li>
<li>Liangtao Shi, Yong Xiao, Yun Shao, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>,
"<A HREF="https://ieeexplore.ieee.org/document/9856889/">Using Mixed Logic Synthesis Tools in Open-Source FPGA Design Framework</a>",
<strong>CSTIC' 22</strong>, <i> China Semiconductor Technology International Conference</i>, Mar
2022, Hangzhou, China. </li>
<h3> 2021 </h3>
<p class="big">
<li>
储著飞,王伦耀,夏银水,"<A HREF="https://kns.cnki.net/kcms/detail/detail.aspx?dbcode=CJFD&dbname=CJFDLAST2022&filename=WNDZ202102009&uniplatform=NZKPT&v=_El82ADdqgNbVp5AMgwZhyulUs-dshiUQttIuWQgT_wsDkSjI_rbpqIctDSEoTOG">基于多逻辑域的逻辑综合研究进展</a>",<i>微纳电子与智能制造</i>,2021, 3(2):64-73. (<strong>Invited</strong>)
</li>
<li>
Hongyang Pan and <A HREF="https://zfchu.github.io/">Zhufei
Chu</a>, "A Semi-Tensor Product Based SAT All Solutions Solver",
<strong>CCFDAC'21</strong>, CCF Integrated
Circuit Design and Automation Conference, Oct. 2021, Wuhan, China. (<strong>Best Paper Award</strong>) <span class="red-star">★</span>
</li>
<li>Hui-Ming Tian and <A HREF="https://zfchu.github.io">Zhu-Fei
Chu</a>, "<A HREF="http://jcst.ict.ac.cn/EN/10.1007/s11390-021-0898-7">Inversion Optimization Strategy based on Primitives
with Complement Attributes</a>", <i>Journal of Computer Science and
Technology (<strong>JCST</strong>)</i>, Sep. 2021, 36(5):1145-1154.
<li>Xiao-Jing Zha, Yin-Shui Xia, Shang-Luan Xie, and <A HREF="https://zfchu.github.io">Zhu-Fei
Chu</a>, "<A HREF="http://jcst.ict.ac.cn/EN/10.1007/s11390-021-0904-0">Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization</a>", <i>Journal of Computer Science and
Technology (<strong>JCST</strong>)</i>, Sep. 2021, 36(5):1118-1132.
<li> Jianguo Ni, and <A HREF="https://zfchu.github.io">Zhufei
Chu</a>, "<A HREF="https://ieeexplore.ieee.org/document/9620355/">An Efficient Demultiplexer Design in Quantum-dot Cellular Automata</a>", <strong> ASICON'21 </strong>, <i>IEEE 14th International Conference on ASIC</i>, Oct. 2021, Virtual online.
<li> Chuanhe Shang, and <A HREF="https://zfchu.github.io">Zhufei
Chu</a>, "<A HREF="https://ieeexplore.ieee.org/document/9620344/">Design of Majority Logic Based 4-bit Approximate Subtractors and Its
Application in Divider </a>", <strong> ASICON'21 </strong>, <i>IEEE 14th International Conference on ASIC</i>, Oct. 2021, Virtual online.
<li>Xuan Wang, <A HREF="https://zfchu.github.io">Zhufei Chu</a>, and Weikang Qian, "<A HREF="https://ieeexplore.ieee.org/document/9643580/">MinSC: An Exact Synthesis-Based Method for Minimal Area Stochastic Circuits under Relaxed Error Bound</a>",
<strong>ICCAD' 21</strong>, <i>International Conference On Computer Aided Design</i>, Nov. 2021, Virtual online.
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>,
Zeqiang Li, Yinshui Xia, Lunyao Wang, and Weiqiang Liu, "<A
HREF="https://ieeexplore.ieee.org/document/9311242">BCD Adder Designs based on Three-Input XOR and Majority Gates</a>", <i> IEEE Transactions on Circuits and Systems II:
Express Briefs(<strong>TCAS-II</strong>)</i>,
June 2021, 68(6):1942-1946.
</li>
<li>Huiming Tian, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>,
"<A HREF="https://ieeexplore.ieee.org/document/9461426">A Novel Toffoli Gate Design Using Quantum-dot Cellular Automata</a>",
<strong>CSTIC' 21</strong>, <i> China Semiconductor Technology International Conference</i>, Mar
2021, Shanghai, China. </li>
<li>Xiang He, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>,
"<A HREF="https://ieeexplore.ieee.org/document/9461462">Stochastic Circuit Design Based on Exact Synthesis</a>",
<strong>CSTIC' 21</strong>, <i> China Semiconductor Technology International Conference</i>, Mar
2021, Shanghai, China. </li>
<h3> 2020 </h3>
<p class="big">
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Mathias
Soeken, Yinshui Xia, Lunyao Wang, and Giovanni De Micheli, "<A
HREF="https://ieeexplore.ieee.org/document/8747480">Advanced Functional Decomposition Using Majority and Its
Applications</a>", <i> IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems (<strong>TCAD</strong>)</i>,
August 2020, 39(8):1621-1634.
</li>
<li>
Huiming Tian, <A HREF="https://zfchu.github.io/">Zhufei
Chu</a>, "Inversion Optimization Strategy
based on Primitives with Complement Attribute",
<strong>CCFDAC'20</strong>, CCF Integrated
Circuit Design and Automation Conference, Aug. 2020, Beijing, China.
</li>
<li> <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Huiming
Tian, Zeqiang Li, Yinshui Xia, and Lunyao Wang, "<A HREF="https://ieeexplore.ieee.org/document/9061012">A
High-Performance Design of Generalized Pipeline Cellular
Array</a>", IEEE Computer Architecture Letters, Jan.-June 1 2020,
19(1):47-50.</li>
<li>Lin Chen, and <A HREF="https://zfchu.github.io/">Zhufei Chu</a>,
"<A HREF="https://ieeexplore.ieee.org/document/9282401">Towards Optimal Logic Representations for Implication-based
Memristive Circuit</a>", <strong>CSTIC' 20</strong>, <i> China Semiconductor Technology International Conference</i>, Mar
2020, Shanghai, China. </li>
<li>Zeqi Chen, Jianping Hu, Hao Ye, and <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, "<A
HREF="https://www.mdpi.com/2072-666X/11/1/64">T-Channel
Field Effect Transistor with Three Input Terminals
(Ti-TcFET)</a>". Micromachines. Jan. 2020, 11(1):64. </li>
<h3> 2019 </h3>
<p class="big">
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Lei Shi,
Lunyao Wang, and Yinshui Xia, "<A HREF="https://www.sciencedirect.com/science/article/pii/S0167926019301932"> Multi-Objective Algebraic
Rewriting in XOR-Majority Graphs</a>", <i> Integration, the
VLSI Journal</i>, 69:40-49, Sep. 2019.
</li>
<li>Libo Qian, Kefang Qian, Xitao He, <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yidie Ye, Ge
Shi, and Yinshui Xia, "<A HREF="https://ieeexplore.ieee.org/document/8677263">Through Silicon Via based Capacitor and Its Application in
LDO Regulator Design</a>", <i> IEEE Transactions on Very Large
Scale Integration Systems (<strong>TVLSI</strong>)</i>,
27(8):1947-1951, 2019.
</li>
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Winston
Haaswijk, Mathias Soeken, Lunyao Wang, Yinshui Xia, and Giovanni
De Micheli, "<A HREF="https://ieeexplore.ieee.org/document/8702141">Exact Synthesis of Boolean Functions in Majority-of-five Forms</a>",
<strong>ISCAS' 19</strong>, <i> IEEE International Symposium on Circuits and Systems</i>, May
2019, Sapporo, Japan.
</li>
<li>Lei Shi, and <A HREF="https://zfchu.github.io/">Zhufei
Chu</a>, "<A HREF="https://ieeexplore.ieee.org/document/8755713">Inversions Optimization in
XOR-Majority Graphs with an Application to QCA</a>",
<strong>CSTIC' 19</strong>, <i> China Semiconductor Technology International Conference</i>, Mar
2019, Shanghai, China.
</li>
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Mathias Soeken, Yinshui
Xia, Lunyao Wang and Giovanni De Micheli, "<A HREF="https://dl.acm.org/citation.cfm?id=3287671">Structural Rewriting in XOR-Majority Graphs </a>",
<strong>ASPDAC' 19</strong>, <i>Asia and South Pacific Design Automation
Conference</i>, Jan 2019, Tokyo, Japan.
</li>
<li>Qiuhong Ying, Lunyao Wang, <A
HREF="https://zfchu.github.io/">Zhufei Chu</a>, and Yinshui Xia, "<A HREF="https://ieeexplore.ieee.org/abstract/document/8983435">Area Optimization of MPRM Circuits Using Approximate Computing</a>",
<strong>ASICON' 19</strong>, <i>International Conference on
ASIC</i>, Oct 2019, Chongqing, China.
</li>
<h3> 2018 </h3>
<p class="big">
<li>Qi Yu, Lunyao Wang, <A HREF="https://zfchu.github.io/">Zhufei
Chu</a>, and Yinshui Xia , "<A
HREF="https://ieeexplore.ieee.org/abstract/document/8565775">
Approximate Computing for 4-bit Adder Design
</a>",
<strong>ICSICT' 18</strong>, <i>The 14th International Conference on Solid-State and Integrated
Circuit Technology</i>, Oct. 2018, Qingdao, Shandong, China.
</li>
<li>Zeqiang Li, <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yinshui
Xia and Lunyao Wang, "<A HREF="https://ieeexplore.ieee.org/abstract/document/8565642">Efficient Design of Decimal Full Adder Using Quantum-dot Cellular Automata </a>",
<strong>ICSICT' 18</strong>, <i>The 14th International Conference on Solid-State and Integrated
Circuit Technology</i>, Oct. 2018, Qingdao, Shandong, China.
</li>
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Mathias Soeken, Yinshui
Xia and Lunyao Wang, "Structural Rewriting in XOR-Majority Graphs </a>",
<strong>IWLS' 18</strong>, <i>International Workshop on Logic & Synthesis</i>, June 2018, San
Francisco, CA, USA.
</li>
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Mathias Soeken, Yinshui
Xia and Giovanni De Micheli, "<A
HREF="http://ieeexplore.ieee.org/document/8297400/">Functional Decomposition
Using Majority</a>",
<strong>ASPDAC' 18</strong>, <i>Asia and South Pacific Design Automation
Conference</i>, Jan 2018, Jeju Island, Korea.
</li>
<h3> 2017 </h3>
<p class="big">
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Mathias Soeken, Yinshui
Xia and Giovanni De Micheli, "<A
HREF="http://www.iwls.org/iwls2017/program.php">Functional Decomposition
Using Majority</a>",
<strong>IWLS' 17</strong>, <i>International Workshop on Logic & Synthesis</i>, June 2017, Austin, TX, USA.
</li>
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Xifan Tang, Mathias
Soeken, Ana Petkovska, Grace Zgheib, Luca Amaru, Yinshui Xia, Paolo Ienne,
Giovanni De Micheli and Pierre-Emmanuel Gaillardon, "<A
HREF="http://dl.acm.org/citation.cfm?id=3060432&CFID=765266662&CFTOKEN=93643535">Improving
Circuit Mapping Performance Through MIG-based Synthesis for Carry
Chains</a>", <strong>GLSVLSI' 17</strong>, <i>ACM Great Lakes Symposium on VLSI</i>, May 2017, Banff, Alberta, Canada.
</li>
<li>
Jibo Wang, Yinshui Xia, <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, and Lunyao Wang, "Fast Cells Defect-Tolerant Mapping Based on Gate Node Interval Selection in CMOL Circuits", <i> Journal of Computer-Aided Design and Computer graphics</i>, 29(1):172-179, Jan 2017. (in Chinese)
</li>
<h3> 2016 </h3>
<p class="big">
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yinshui Xia, Lunyao Wang and Jian Wang, "<a href="http://onlinelibrary.wiley.com/doi/10.1002/cta.2178/full"> Efficient power pad assignment for multi-voltage SoC and its application in floorplanning</a>", <i>International Journal of Circuit Theory and Applications</i>, 44(8): 1533–1550, 2016.</li>
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yinshui Xia and Lunyao Wang, "<a href="http://www.sciencedirect.com/science/article/pii/S0167926015001170"> Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence </a>", <i>Integration, the VLSI Journal</i>, 52:335-346, Jan 2016.</li>
<h3> 2014 </h3>
<p class="big">
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yinshui Xia, Lunyao Wang and Jian Wang, "<a href="http://www.sciencedirect.com/science/article/pii/S002626921400007X">Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine</a>", <i>Microelectronics Journal</i>, 45(4):382-393, Apr. 2014. </li>
<li> <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yinshui Xia, Lunyao Wang, and Jun Zhai "Wire-bonding Power Pad Assignment and Power Mesh Topological Optimization for Multiple Voltage SoC", <i> Journal of Computer-Aided Design and Computer graphics</i>, 26(9):1501-1508, Sep 2014. </li>
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yinshui Xia, Lunyao Wang, "<a href="http://dl.acm.org/citation.cfm?id=2591587"> Level shifter planning for timing constrained multi-voltage SoC floorplanning </a>", <strong>GLSVLSI' 14</strong>, <i>ACM Great Lakes Symposium on VLSI</i>, May 2014, Houston, USA, pp.329-334.</li>
<h3> Before 2014 </h3>
<p class="big">
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yinshui Xia,William N. N. Hung, Xiaoyu Song and Lunyao Wang, “<a href="http://www.tandfonline.com/doi/abs/10.1080/00207217.2012.720945"> Timing-driven logic restructuring for nano-hybrid circuits </a>”, International Journal of Electronics, 100(5):669-685, May 2013.</li>
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yinshui Xia and Lunyao Wang, “<a href="https://link.springer.com/article/10.1007/s11390-012-1210-7">Cell mapping for nanohybrid circuit architecture using genetic algorithm</a>”,Journal of Computer Science and Technology, 27(1):113-120, Jan. 2012. </li>
<li>Yinshui Xia, <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, William N. N. Hung, Lunyao Wang and Xiaoyu Song, “<a href="http://ieeexplore.ieee.org/document/5738347/">An integrated optimization approach for nanohybrid circuit cell mapping </a>”,IEEE Transactions on Nanotechnology, 10(6):1275-1284, Nov. 2011. </li>
<li>Lunyao Wang, <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, and Yinshui Xia, "<a href="https://link.springer.com/article/10.1007/s11390-013-1397-2">Low power state assignment algorithm for FSMs considering peak current optimization</a>", Journal of Computer Science and Technology, 28(6):1054-1062, Nov. 2013. </li>
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yinshui Xia, Lunyao Wang and Jian Wang, "Voltage drop aware power pad assignment and floorplanning for multi-voltage SoC designs", <i>13th International Conference on Computer-Aided Design and Computer Graphics (<strong>CAD/Graphics 2013</strong>)</i>, Nov. 2013, Hongkong, pp. 87-94. </li>
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yinshui Xia, William N. N. Hung, Lunyao Wang and Xiaoyu Song , “A memetic approach for nanoscale circuit cell mapping”,<i>13th EUROMICRO Conference on Digital System Design (<strong>DSD 2010</strong>)</i>, Sep. 2010, Lille, France. </li>
<li><A HREF="https://zfchu.github.io/">Zhufei Chu</a>, Yinshui Xia, Lunyao Wang and Meiqun Hu, “CMOL cell assignment based on dynamic interchange”,<i>Proceedings 2009 8th IEEE International Conference on ASIC (<strong>ASICON 2009</strong>)</i>,Oct. 2009, Changsha, China. </li>
<li> Yinshui Xia, <A HREF="https://zfchu.github.io/">Zhufei Chu</a>, William N. N. Hung, Lunyao Wang and Xiaoyu Song, “CMOL cell assignment by genetic algorithm”,<i>8th IEEE NEWCAS Conference (<strong>NEWCAS 2010</strong>)</i>,Jun. 2010, Montreal, Canada. </li>
<li>Zhufei Chu, Yinshui Xia and Lunyao Wang, "Fast mapping of Nano/CMOS cells", <i> Journal of Computer-Aided Design and Computer graphics</i>, 23(3):514-520, Mar 2011.</li>
<li>Yinshui Xia, Zhufei Chu, Lunyao Wang, William N N Hung and Xiaoyu Song, "Logic Equivalent Transformation for Nano-meter CMOS Hybrid Circuits", <i> Journal of Electronics and Information Technology</i>, 33(7):1733-1737, July 2011.</li>
</OL>
<HR>
<h2><a name="services">Professional Services</a></h2>
<ul>
<p class="big">
<li>General Chair for the International Workshop on Logic and Synthesis, 2026.</li>
<li>Proceedings Chair, TPC member, and Session Chair for the International Workshop on Logic and Synthesis, 2019-2021.</li>
<li>Finance Chair, TPC member, and Session Chair for the International
Workshop on Logic and Synthesis, 2022-2023.</li>
<li>TPC member for the International
Workshop on Logic and Synthesis, 2024-2025.</li>
<li>Digital Design & Verification Track Chair of the IEEE International Symposium of EDA, 2023-2024.</li>
<li>High-Level, Behavioral, and Logic Synthesis and Optimization Track Chair of the IEEE International Symposium of EDA, 2025.</li>
<li>TPC Chair for the International Conference on Circuits and Systems
(ICCS), 2023, 2025.</li>
<li>Editorial Board Member for the Journal of Electronics and Information Technology (JEIT), 2023-2026 </li>
<li>TPC member for the Design Automation Conference, 2023-2025.</li>
<li>TPC member for the Design, Automation and Test in Europe Conference, 2024.</li>
<li>TPC member for the International Conference on VLSI Design, 2020-2022. </li>
<li>TPC member for the China Semiconductor Technology International Conference (Symposium IX), 2021-2025. </li>
<li>TPC member for the IFIP/IEEE International Conference on Very Large Scale Integration (PhD Forum), 2020. </li>
<li>TPC member for the IEEE International Conference on Computer Design (Special Sessions), 2020. </li>
<li>TPC member for the IEEE International Conference on Omni-layer Intelligent systems, 2019-2020. </li>
<li>TPC member and Session Chair for the CCF Integrated Circuit Design and
Automation Conference, 2020-2023. </li>
<li>Reviewer for the journal IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. </li>
<li>Reviewer for the journal IEEE Transactions on Very Large Scale Integration (VLSI) Systems. </li>
<li>Reviewer for the journal IEEE Transactions on Information Forensics and Security. </li>
<li>Reviewer for the journal IEEE Transactions on Emerging Topics in Computing. </li>
<li>Reviewer for the journal IEEE Transactions on Circuits and Systems-Part I. </li>
<li>Reviewer for the journal IEEE Transactions on Circuits and Systems-Part II. </li>
<li>Reviewer for the journal IEEE Transactions on Information Forensics & Security. </li>
<li>Reviewer for the journal ACM Transactions on Design Automation of Electronic Systems. </li>
<li>Reviewer for the journal IET Circuits, Devices & Systems. </li>
<li>Reviewer for the journal Journal of Computer Science and Technology. </li>
<li>Reviewer for the journal Integration, the VLSI Journal. </li>
<li>Reviewer for the journal Microelectronics Journal. </li>
<li>Reviewer for the journal International Journal of Circuit Theory and Applications. </li>
<li>Reviewer for the journal IET Quantum Communication. </li>
<li>Reviewer for the journal IET Computers & Digital Techniques. </li>
<li>Reviewer for the journal Optik, International Journal for Light and Electron Optics. </li>
<li>Reviewer for the journal Journal of Combinatorial Optimization. </li>
<li>Reviewer for the journal Journal of Supercomputing. </li>
<li>Reviewer for the journal The Computer Journal. </li>
<li>Reviewer for the journal Theoretical Computer Science.</li>
</ul>
<h2><a name="links">Links</a></h2>
<ul>
<li><a href="http://www.cse.chalmers.se/research/group/vlsi/conference/">VLSI
Conference Table</a>, <a href="http://www.ieee-ceda.org/">CEDA</a>,
<a href="http://ieeexplore.ieee.org/Xplore/dynhome.jsp">Xplore</a>
</li>
</ul>
<table border="0" cellspacing="5">
<tbody>
<tr>
<td width="500">
<h2>
<a name="address">Address</a>
</h2>
Yuxiu Road 505, Zhenhai, Ningbo, 315211<br>
Faculty of Electrical Engineering and Computer Science (EECS)<br>
Ningbo University, Zhejiang, China</td>
<td></td>
<td width="500"></td>
<td></td>
<td width="450">
<img src="images/yangym.jpg" width="420">
</td>
</td>
<td width="500"></td>
<td></td>
<td width="450">
<img src="images/group.jpeg" width="420">
</td>
</tr>
</tbody>
</table>
</BODY>
</HTML>