Phoenix promontory 21

Include/xSIM-api.h

@@ -70,6 +70,7 @@ typedef enum {
   SilId_RasClass,
   SilId_ApobClass,
   SilId_GfxClass,
+  SilId_PromClass,
   // Add new elements above this line ^^^
   SilId_ListEnd             ///< Value to bound the list
 } SIL_DATA_BLOCK_ID;

xSIM/SoC/F19M70/IpBlkListF19M70Tp1.c

@@ -29,6 +29,8 @@
 #include <FCH/Tacoma/FchCore/FchSd/FchSdTc.h>
 #include <APOB/PHX/ApobPhx.h>
 #include <MEM/Phx/MemPhx.h>
+#include <PROM/PromClass-api.h>
+#include <PROM/Common/PromInit.h>
 
 
 /**
@@ -59,7 +61,7 @@
  *          - MPIO:   MPIO firmware initializes and trains the PCIe links
  *                    (required for CXL). Due to this dependency,
  *                    MPIO is initialized prior to CXL IP block.
- *          - CXL:    CXL is dependent on MPIO and is initialized after MPIO.
+ *          - PROM:   PROM is dependent on MPIO and is initialized after MPIO.
  */
 const SOC_IP_TABLE SocIpTblF19M70Tp1 = {
   AMD_FAMILY_19_PHX,     // This is the 'Client' F19M70  a.k.a. Phoenix
@@ -181,6 +183,13 @@ const SOC_IP_TABLE SocIpTblF19M70Tp1 = {
       InitializeCcxZen4PhxTp1,
       InitializeApiZen4Phx
     },
+    {
+      SilId_PromClass,
+      PROMCLASS_DATA_SIZE,
+      PromClassSetInputBlock,
+      InitializePromTp1,
+      NULL,
+    },
     {SilId_ListEnd, 0, NULL, NULL, NULL}  // End of list marker
   }
 };

xUSL/FCH/Common/FchCommon.c

@@ -29,7 +29,6 @@ SilFchStall (
   uint16_t TimerAddr;
   uint32_t StartTime;
   uint32_t ElapsedTime;
-  FCH_TRACEPOINT(SIL_TRACE_ENTRY, "\n");
 
   SilFchReadPmio(FCH_PM_ACPIPMTMRBLK, AccessWidth16, (uint8_t *)&TimerAddr);
   if ((TimerAddr == 0) || (TimerAddr == 0xFFFF)) {
@@ -52,7 +51,6 @@ SilFchStall (
       }
     }
   }
-  FCH_TRACEPOINT(SIL_TRACE_EXIT, "\n");
 }
 
 /**

xUSL/Include/Pci.h

@@ -12,8 +12,6 @@
 
 #include "stdint.h"
 
-#define PCIE_CAP_ID      0x10
-
 #define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((uint32_t) (Seg)) << 28) | (((uint32_t) (Bus)) << 20) | \
         (((uint32_t)(Dev)) << 15) | (((uint32_t)(Fun)) << 12) | ((uint32_t)(Off)))
 
@@ -87,3 +85,17 @@ void xUSLPciWrite (uint32_t Address, ACCESS_WIDTH Width, void *Value);
 #define PCI_HEADER_TYPE_REG       (0x0E)
 #define MULTI_FUNC_DEVICE_MASK    (BIT_32(7))
 #define PCI_REVISION_ID_REG       (0x08)
+
+//
+// PCI Express Capability Structure
+//
+#define PCIE_CAP_ID                           0x10
+
+#define PCIE_LINK_CAP_REG                     0x0C // Link Capabilities Register (Offset 0Ch)
+#define PCIE_LINK_CONTROL_REG                 0x10 // Link Control Register      (Offset 10h)
+#define PCIE_LINK_STATUS_REG                  0x12 // Link Status Register       (Offset 12h)
+#define PCIE_SLOT_STATUS_REG                  0x1A // Slot Status Register       (Offset 1Ah)
+
+#define PCIE_DEVICE_CAP2_REG                  0x24 // Device Capabilities 2 Register (Offset 24h)
+#define PCIE_DEVICE_CONTROL2_REG              0x28 // Device Control 2 Register      (Offset 28h)
+#define PCIE_LINK_CONTROL2_REG                0x30 // Link Control 2 Register        (Offset 30h)

xUSL/Include/SilCommon.h

@@ -76,6 +76,7 @@
 #define DEBUG_FILTER_CXL        0x00000200UL
 #define DEBUG_FILTER_RCMGR      0x00000800UL
 #define DEBUG_FILTER_GFX        0x00001000UL
+#define DEBUG_FILTER_PROM       0x00002000UL
 // set the default Module filter, allowing the Host to pre-define
 #ifndef SIL_DEBUG_MODULE_FILTER
   #define SIL_DEBUG_MODULE_FILTER      ( DEBUG_FILTER_APOB | \
@@ -88,7 +89,8 @@
           DEBUG_FILTER_FCH | \
           DEBUG_FILTER_CXL | \
           DEBUG_FILTER_RCMGR | \
-          DEBUG_FILTER_GFX )
+          DEBUG_FILTER_GFX | \
+          DEBUG_FILTER_PROM)
 #endif
 
 /** Message type enables

xUSL/Mpio/Common/MpioCmn2Rev.h

@@ -168,6 +168,20 @@ typedef SIL_STATUS (*MPIO_PCIE_SET_SPEED) (
   uint8_t                       TargetSpeed
   );
 
+typedef struct {
+  bool      EarlyLinkStatus;
+  uint8_t   PhysicalRootBridge;
+  uint8_t   LogicalRootBridge;
+  uint8_t   RootPortBus;
+  uint8_t   RootPortDevice;
+  uint8_t   RootPortFunction;
+} EARLY_LINK_STATUS;
+
+typedef SIL_STATUS (*MPIO_GET_EARLY_LINK_CONFIG) (
+  SIL_CONTEXT                   *SilContext,
+  EARLY_LINK_STATUS             *EarlyLinkStatus
+  );
+
 // Define the Cmn2Rev xfer table containing pointers to these functions
 
 typedef struct {
@@ -200,4 +214,5 @@ typedef struct {
   MPIO_GET_PORT_ID                  MpioGetPortId;
   MPIO_REMOVE_CXL_LINKS             MpioRemoveCxlLinks;
   MPIO_PCIE_SET_SPEED               MpioPcieSetSpeed;
+  MPIO_GET_EARLY_LINK_CONFIG        MpioGetEarlyLinkConfig;
 } MPIO_COMMON_2_REV_XFER_BLOCK;

xUSL/Mpio/Phx/MpioCmn2Phx.c

@@ -38,5 +38,6 @@ MPIO_COMMON_2_REV_XFER_BLOCK MpioXferPhx = {
   .MpioReleasePort = MpioReleasePortPhx,
   .MpioGetPortId = MpioGetPortIdPhx,
   .MpioRemoveCxlLinks = MpioRemoveCxlLinksPhx,
-  .MpioPcieSetSpeed = MpioPcieSetSpeed
+  .MpioPcieSetSpeed = MpioPcieSetSpeed,
+  .MpioGetEarlyLinkConfig = MpioGetEarlyLinkConfig
 };

xUSL/Mpio/Phx/MpioCmn2Phx.h

@@ -11,9 +11,9 @@
 
 #include <SilCommon.h>
 #include <Nbio/Common/GnbDxio.h>
+#include <Mpio/Common/MpioCmn2Rev.h>
 #include <Mpio/MpioClass-api.h>
 
-
 void
 MpioCfgGlobalConfigPhx (
   SIL_CONTEXT                   *SilContext,
@@ -205,4 +205,10 @@ MpioPcieSetSpeed (
   uint8_t                       PciDevice,
   uint8_t                       PciFunction,
   uint8_t                       TargetSpeed
-  );
+  );
+
+SIL_STATUS
+MpioGetEarlyLinkConfig (
+  SIL_CONTEXT                   *SilContext,
+  EARLY_LINK_STATUS             *EarlyLinkStatus
+  );

xUSL/Mpio/Phx/MpioInitPhx.c

@@ -12,6 +12,7 @@
 #include <Nbio/Phx/includePHX/PHX_GnbRegistersPhx.h>
 #include <Nbio/Phx/includePHX/PHX_NBIFMM.h>
 #include <Mpio/MpioClass-api.h>
+#include <Mpio/Common/MpioCmn2Rev.h>
 #include <Mpio/Common/MpioLib.h>
 #include <APOB/Common/ApobCmn.h>
 #include <string.h>
@@ -616,7 +617,7 @@ MpioPcieSetSpeed (
   StartLaneId = 0xFF;
   EndLaneId = 0xFF;
 
-  PcieWrapper = (PCIe_WRAPPER_CONFIG *) NbioIp2Ip->PcieConfigGetChild(DESCRIPTOR_ALL_WRAPPERS, &Pcie->Header);
+  PcieWrapper = (PCIe_WRAPPER_CONFIG *) NbioIp2Ip->PcieConfigGetChild(DESCRIPTOR_ALL_WRAPPERS, &(GnbHandle->Header));
   while (PcieWrapper != NULL) {
     PcieEngine =(PCIe_ENGINE_CONFIG *)(NbioIp2Ip->PcieConfigGetChild(DESCRIPTOR_ALL_ENGINES, &(PcieWrapper->Header)));
     while (PcieEngine != NULL) {
@@ -655,3 +656,73 @@ MpioPcieSetSpeed (
 
   return Status;
 }
+
+static void
+FindEarlyLink (
+  SIL_CONTEXT           *SilContext,
+  PCIe_ENGINE_CONFIG    *Engine,
+  void                  *Buffer,
+  PCIe_PLATFORM_CONFIG  *Pcie
+  )
+{
+  GNB_HANDLE            *GnbHandle;
+  EARLY_LINK_STATUS     *EarlyLinkStatus;
+
+  if (Engine->Type.Port.PortData.MiscControls.SbLink == 1) {
+    if (Engine->InitStatus == INIT_STATUS_PCIE_TRAINING_SUCCESS) {
+      EarlyLinkStatus = (EARLY_LINK_STATUS *)Buffer;
+      EarlyLinkStatus->EarlyLinkStatus = true;
+      GnbHandle = (GNB_HANDLE *)PcieConfigGetParentSilicon(Engine);
+      EarlyLinkStatus->PhysicalRootBridge = GnbHandle->RBIndex;
+      EarlyLinkStatus->LogicalRootBridge = GnbHandle->LogicalRBIndex;
+      EarlyLinkStatus->RootPortBus = (uint8_t) GnbHandle->Address.Address.Bus;
+      EarlyLinkStatus->RootPortDevice = Engine->Type.Port.PortData.DeviceNumber;
+      EarlyLinkStatus->RootPortFunction = Engine->Type.Port.PortData.FunctionNumber;
+    }
+  }
+}
+
+SIL_STATUS
+MpioGetEarlyLinkConfig (
+  SIL_CONTEXT                   *SilContext,
+  EARLY_LINK_STATUS             *EarlyLinkStatus
+  )
+{
+  PCIe_PLATFORM_CONFIG          *Pcie;
+  NBIO_IP2IP_API                *NbioIp2Ip;
+  NORTH_BRIDGE_PCIE_SIB         *NbPcieData;
+
+  MPIO_TRACEPOINT(SIL_TRACE_ENTRY, "\n");
+
+  if (SilGetIp2IpApi(SilContext, SilId_NbioClass, (void **)(&NbioIp2Ip)) != SilPass) {
+    MPIO_TRACEPOINT(SIL_TRACE_ERROR, " NBIO API is not found.\n");
+    return SilNotFound;
+  }
+  NbPcieData = (NORTH_BRIDGE_PCIE_SIB *)xUslFindStructure(SilContext,
+                                          SilId_NbioClass,
+                                          NBIOPCIECLASS_INSTANCE);
+  if (NbPcieData == NULL) {
+    MPIO_TRACEPOINT(SIL_TRACE_ERROR, " NBIO Pcie config not found.\n");
+    return SilNotFound;
+  }
+
+  Pcie = &NbPcieData->PciePlatformConfig;
+
+  EarlyLinkStatus->EarlyLinkStatus = false;
+  EarlyLinkStatus->PhysicalRootBridge = 0;
+  EarlyLinkStatus->LogicalRootBridge = 0;
+  EarlyLinkStatus->RootPortBus = 0;
+  EarlyLinkStatus->RootPortDevice = 0;
+  EarlyLinkStatus->RootPortFunction = 0;
+
+  NbioIp2Ip->PcieConfigRunProcForAllEngines(SilContext,
+    DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
+    FindEarlyLink,
+    EarlyLinkStatus,
+    Pcie
+    );
+
+  MPIO_TRACEPOINT(SIL_TRACE_EXIT, "\n");
+
+  return SilPass;
+}

xUSL/Nbio/Common/Nbio.c

@@ -383,6 +383,17 @@ NbioIoApicInit (
     }
   } else {
     NBIO_TRACEPOINT(SIL_TRACE_INFO, "We don't need reserved IOAPIC MMIO space\n");
+    if (NbioIpBlockData->NbioConfigData.CfgGnbIoapicAddress != 0) {
+      NBIO_TRACEPOINT(SIL_TRACE_INFO, "Using fixed IOAPIC MMIO address %x\n",
+        NbioIpBlockData->NbioConfigData.CfgGnbIoapicAddress);
+      GnbHandle = GetGnbHandle(SilContext);
+      if (GnbHandle) {
+        NbioXfer->NbioIoApicMmioAddress(
+          GnbHandle,
+          NbioIpBlockData->NbioConfigData.CfgGnbIoapicAddress
+          );
+      }
+    }
   }
 
   if (NbioIpBlockData->NbioConfigData.IoApicIdPreDefineEn) {

xUSL/Nbio/Common/NbioData.c

@@ -18,6 +18,7 @@ const NBIO_CONFIG_DATA mNbioConfigDataDflts = {
   .IoApicMMIOAddressReservedEnable = CONFIG_IOAPIC_MMIO_ADDRESS_RESERVED_ENABLE,
   .IoApicIdPreDefineEn = CONFIG_IOAPIC_ID_PREDEFINE_EN,
   .IoApicIdBase = CONFIG_IOAPIC_ID_BASE,
+  .CfgGnbIoapicAddress = 0,
   .NbifMgcgHysteresis = CONFIG_NBIF_MGCG_HYSTERESIS,
   .SyshubMgcgHysteresis = CONFIG_SYSHUB_MGCG_HYSTERESIS,
   .IohcNonPCIBarInitSmu = CONFIG_IOHC_NONPCI_BAR_INIT_SMU,

xUSL/Nbio/NbioClass-api.h

@@ -46,6 +46,7 @@ typedef struct {
   bool IoApicMMIOAddressReservedEnable; ///< Enable Ioapic MMIO reserved from GNB driver. 0:Disable
   bool IoApicIdPreDefineEn;             ///< Enable assign IOAPIC ID
   uint8_t IoApicIdBase;                 ///< Base NBIO IOAPIC ID. ID assigned start from this value */
+  uint64_t CfgGnbIoapicAddress;         ///< Fixed Ioapic MMIO address if not reserved from RcMGr. 0:Disable
   uint8_t NbifMgcgHysteresis;           ///< NBIF MGCG HYSTERESIS for gating count
   uint8_t SyshubMgcgHysteresis;         ///< NBIF MGCG HYSTERESIS for gating count
   bool IohcNonPCIBarInitSmu;            ///< Configure non pci device bar for SMU