CSE Bubble Processor

• PDS1

  We plan to use 1024 registers, each of which stores 32 bit words. The instructions and words are loaded into these registers.

• PDS2

  We are using 1024 of 8 byte (32 bit) memory elements in instruction memory to hold the instructions. Similarly, we use 1024 of 8 byte memory elements in data memory to store words.

• PDS3

  We use the instruction encoding identical to MIPS standard. That is, opcode (of 6 bits) of 0 for R type instruction, followed by four 5 bit blocks for source1, source2, dest and shift, followed by 6 bits for funct. Similarly an opcode of 2 for J type instruction followed by 26 bits for the address of the instruction. We use format of 6 bit opcode, and 16 bit address in the end for L type instructions.

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ALU Instruction Set

Instruction	Opcode	Funct
add	0	32
addi	0	33
sub	0	34
subi	0	35
and	0	36
or	0	37
sll	0	0
srl	0	2
beq	3	NA
bne	4	NA
bgt	5	NA
bgte	6	NA
blt	7	NA
bleq	8	NA