VES-369 is a high-velocity IP package consisting of a JavaScript engine, a header-only C++ library, and a SystemVerilog RTL decoder designed to optimize data transmission through vibrational frequency mapping. Inspired by the 3-6-9 mathematical principles of Nikola Tesla, this protocol bypasses 8-bit ASCII inefficiencies to reclaim dead space in data streams across the edge, systems, and silicon.
Unlike traditional dictionary-based compressors (ZIP/GZIP) that require large histories to function, VES-369 uses a Lattice-based Waterfall. Data "falls" through three distinct vibrational phases:
- L3 Core (01 Phase): Top 8 most frequent characters compressed to 5 bits.
- L6 Mid (10 Phase): Next 64 characters mapped to 8 bits.
- L9 Outlier (11 Phase): Remaining characters mapped to 9 bits.
Verified via included industrial testbenches.
| Metric | Specification |
|---|---|
| Algorithm Type | Deterministic Lattice Mapping |
| Lossless Status | 100% Bit-True Verified |
| Header Overhead | 12 Bytes (8-byte Lattice + 4-byte Bit-Stop) |
| Avg. Reduction | 24% - 37% (Data Dependent) |
| Platform Parity | SystemVerilog ↔ C++ ↔ JavaScript |
DNA data is perfectly suited for the Vortex Lattice. By locking A, C, G, and T into the L3 Core, VES-369 achieves a 37.5% reduction in raw sequence data footprints—saving petabytes of storage for research institutions.
Optimized for the NASA/NVIDIA telemetry standard. Reduce packet sizes for orbital transmission without the CPU overhead of traditional compression. Asymmetric architecture enables low-power satellites to stream vibrated data that is reconstructed instantly in ground-station hardware.
Massive reduction for numerical transaction logs. Reclaim 20-25% of database storage costs by vibrating numeric strings into the 5-bit L3 Core. In High-Frequency Trading (HFT), the zero-latency hardware decoder enables more market updates per packet and faster trade execution by reducing the compression penalty.
- 🚀
VES-369_engine.hpp: The C++ engine. Header-only, zero dependencies. - 🌐
VES-369_engine.js: Web-integration layer for Node.js and browser parity. - 🛰️
VES-369_decoder.sv: SystemVerilog RTL. Combinational, zero-jitter hardware decoder. - 💻
VES-369_simulator.html: Live visual dashboard for bit-stream analysis. - ⚙️
VES-369_testbench.*: Industrial C++, JS, and SV verification suites.
VES-369 is available under a dual-licensing model to balance community innovation with high-performance industrial needs.
- Open Source (AGPL-3.0): Ideal for public research, open-source infrastructure, and community-driven projects. This license requires that any derivative works or network-hosted versions of the protocol remain open-source.
- Commercial License: Required for closed-source applications, proprietary hardware synthesis (ASIC/FPGA), or integration into private enterprise platforms. This license provides an exemption from the AGPL copyleft requirements and includes options for technical integration support.
For commerical licensing inquiries please contact:
Licensing Agent - J.E. Randolph 📧 700josh.r@gmail.com
Copyright © 2026 Jonathan Alan Reed. Software provided under AGPL-3.0. Commercial use requires a separate license agreement.
