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feat(settings): raise the configurable motor pole-count ceiling to 128 - #83

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feat(settings): raise the configurable motor pole-count ceiling to 128#83
AlexKlimaj wants to merge 1 commit into
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claude/motor-pole-count-limit-54ai7l

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What

Raises the maximum motor pole count a user can configure from 64 to 128 (64 pole pairs), and gives the range names — MOTOR_POLES_MIN / MOTOR_POLES_MAX in Inc/eeprom.h — instead of the open-coded 2..64 that was repeated in three places.

Note on the 36: there is no 36-pole limit anywhere in this firmware. That cap comes from the configurators; the firmware-side ceiling was 64, set by the DroneCAN MOTOR_POLES parameter and mirrored by the two kv-derived schedules in settings.c. Both still excluded large direct-drive / hub motors, so this raises the firmware ceiling well clear of 36 and of 64. 128 stays below the 0xff an erased eeprom reads, so out-of-range detection (0 or 0xff → schedules fall back) is unchanged.

Changes

  • Inc/eeprom.hMOTOR_POLES_MIN (2) / MOTOR_POLES_MAX (128), documented against eeprom byte 27.
  • Src/DroneCAN/DroneCAN.cMOTOR_POLES parameter uses the macros, so the DroneCAN GUI now offers the full range.
  • Src/settings.c — both gates use the macros. Above 64 poles the two schedules now compute instead of falling back to their "implausible pole count" behavior:
    • throttle-restriction envelope: worst case 10220 kv * 128 poles / 544 = 2405 kerpm, well inside the uint16 the levels live in.
    • advance normalization: kv * poles * 4096 / 200000 overflows uint32 above ~102 poles, so the reduced 256 / 12500 form is evaluated instead. Same rational number (both terms divided by 16) and it truncates to the same integer for every accepted kv/pole pair, but the intermediate stays in uint32 across the whole byte range (10220 * 255 * 256 = 6.7e8 against 4.29e9). Worst-case scale becomes 53372, leaving the 15/16 scale-down, the uint16 it lands in, and the hot path's (scale * centivolts) >> 12 on a 12S pack all in range.
  • Mcu/SITL/sitl_params.py, Mcu/SITL/sitl_gui.py, scripts/esc_capture_gui.py — pole-count ranges that mirrored the old 64 raised to 128.

No behavior change at or below 64 poles: the gates accept exactly what they did before, and the rewritten scale expression is bit-identical over the accepted kv range (checked exhaustively over poles 2..255 against the old form).

Test

  • make AM32_SITL_CAN builds clean; make check_format reports only the four pre-existing offenders under Mcu/ (untouched here).
  • SITL end-to-end (AM32_SITL_CAN, heavy_13inch model at 360 kv, DShot300, throttle 900): 46-pole and 120-pole configs both arm, start, and hold closed loop — 3545 rpm and 3427 rpm respectively — so the newly enabled envelope and advance normalization do not disturb startup or run.
  • The DroneCAN parameter test (Mcu/SITL/tests/test_params.py) was not run: pytest/dronecan are not installed in this container.

Not changed: nothing clamps motor_poles itself, so an erased-eeprom 0 would still divide by zero in the sine-startup step delay and the rpm speed-control path. Pre-existing and out of scope here, but worth a follow-up.


Generated by Claude Code

The pole count a user can enter was capped at 64 by the DroneCAN
MOTOR_POLES parameter and by the two kv-derived schedules in
settings.c, and configurators have historically stopped at 36. That
excludes large direct-drive and hub motors, whose pole counts run well
past both.

Give the range names (MOTOR_POLES_MIN / MOTOR_POLES_MAX in eeprom.h)
and raise the ceiling to 128 poles - 64 pole pairs, still below the
0xff an erased eeprom reads so out-of-range detection is unchanged -
and use the names in the DroneCAN parameter table and in both gates in
settings.c instead of the open-coded 2..64.

Above 64 poles the two schedules that gate on the range now compute
instead of falling back:

  - throttle-restriction envelope: worst case 10220 kv * 128 poles /
    544 = 2405 kerpm, well inside the uint16 the levels live in.

  - advance normalization: kv * poles * 4096 / 200000 overflows uint32
    above ~102 poles, so evaluate the reduced 256 / 12500 form. It is
    the same rational number (both terms divided by 16) and truncates
    to the same integer for every accepted kv/pole pair, but its
    intermediate stays in uint32 across the whole byte range
    (10220 * 255 * 256 = 6.7e8 against 4.29e9). Worst case scale
    becomes 53372, which leaves the 15/16 scale-down, the uint16 it
    lands in, and the hot path's (scale * centivolts) >> 12 on a 12S
    pack all in range.

Also raise the pole-count range in the SITL parameter table and the two
Qt spin boxes that mirrored the old 64.

SITL (AM32_SITL_CAN, heavy_13inch model at 360 kv): 46-pole and
120-pole configs both arm, start and hold closed loop under DShot300 at
throttle 900 - 3545 and 3427 rpm respectively - so the newly enabled
envelope and advance normalization do not disturb startup or run.
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