Lab4

task2/task2.v

@@ -0,0 +1,21 @@
+module task2(
+	input signed [3:0] a, b,
+	output reg dout, dout_eq
+	);
+
+	always @(*) begin
+		if (a > b) begin
+			dout = 0;
+			dout_eq = 0;
+		end
+		else if (a == b) begin
+			dout = 0;
+			dout_eq = 1;
+		end
+		else begin
+			dout = 1;
+			dout_eq = 0;
+		end
+	end
+
+endmodule

task2/task2_tb.sv

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+`timescale 1ns/1ns
+
+module task2_tb;
+
+	logic signed [3:0] a, b;
+	logic dout, dout_eq;
+
+	task2 DUT(
+		.a(a),
+		.b(b),
+		.dout(dout),
+		.dout_eq(dout_eq)
+	);
+
+	initial begin
+		a = 4'b1111; b = 4'b0111;
+		#10;
+		a = 4'b0111; b = 4'b0111;
+		#10;
+		a = 4'b0111; b = 4'b0000;
+		#10;
+
+		$stop;
+
+	end
+endmodule

task3/task3.v

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+module task3 (
+	input [23:0] din,
+	input [3:0] sel,
+	output reg [1:0] dout
+	);
+
+	always @(*) begin
+		case (sel)
+			4'd0: dout = din[1:0];
+			4'd1: dout = din[3:2];
+			4'd2: dout = din[5:4];
+			4'd3: dout = din[7:6];
+			4'd4: dout = din[9:8];
+			4'd5: dout = din[11:10];
+			4'd6: dout = din[13:12];
+			4'd7: dout = din[15:14];
+			4'd8: dout = din[17:16];
+			4'd9: dout = din[19:18];
+			4'd10: dout = din[21:20];
+			4'd11: dout = din[23:22];
+			default: dout = 2'b11;
+		endcase
+	end
+
+endmodule

task3/task3_tb.sv

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+`timescale 1ns/1ns
+
+module task3_tb;
+
+	logic [23:0] din;
+	logic [3:0] sel;
+	logic [1:0] dout;
+
+	task3 DUT(
+		.din(din),
+		.sel(sel),
+		.dout(dout)
+	);
+
+	initial begin
+		for (int i = 0; i < 12; i++) begin
+			din[i * 2 +: 2] = i[1:0];
+		end
+
+		for (int i = 0; i < 12; i++) begin
+			sel = i;
+			#10;
+		end
+
+		#10;
+		sel = 4'd12;
+		#10;
+
+		$stop;
+
+	end
+endmodule

task4/task4.v

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+module task4(
+	input [6:0] din,
+	output wire dout
+	);
+
+	wire [2:0] count;
+
+	assign count = din[0] + din[1] + din[2] + din[3] + din[4] + din[5] + din[6];
+
+	assign dout = (count >= 3'd4);
+
+endmodule

task4/task4_tb.sv

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+`timescale 1ns/1ns
+
+module task4_tb;
+
+	logic [6:0] din;
+	logic dout;
+
+	task4 DUT(
+		.din(din),
+		.dout(dout)
+	);
+
+	initial begin
+		din = 7'b1111000;
+		#10;
+		din = 7'b1111100;
+		#10;
+		din = 7'b1110000;
+		#10;
+		$stop;
+
+	end
+endmodule

task5/task5.v

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+module task5(
+	input signed [3:0] a, b,
+	output reg signed [7:0] dout
+	);
+
+	always @(*) begin
+		if (a < 0 || b < 0) begin
+			dout = a + b;
+		end
+		else begin
+			dout = a * b;
+		end
+	end
+
+endmodule

task5/task5_tb.sv

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+`timescale 1ns/1ns
+
+module task5_tb;
+
+	logic signed [3:0] a, b;
+	logic signed [7:0] dout;
+
+	task5 DUT(
+		.a(a),
+		.b(b),
+		.dout(dout)
+	);
+
+	initial begin
+		a = 4'b1111; b = 4'b0111;
+		#10;
+		a = 4'b0111; b = 4'b0111;
+		#10;
+		$stop;
+
+	end
+endmodule