Lab6

lab6/alu_task.sv

@@ -0,0 +1,40 @@
+module alu_task(
+	input logic [31:0] operand_1, operand_2,
+	input logic [2:0] alu_ctrl,
+	output logic [31:0] result,
+	output logic [3:0] flags
+	);
+
+	logic v, c, n, z;
+
+	logic [31:0] add_res, sub_res;
+
+	assign add_res = operand_1 + operand_2;
+	assign sub_res = operand_1 - operand_2;
+
+	always_comb begin
+		case (alu_ctrl)
+			3'b000: result = add_res;
+			3'b001: result = sub_res;
+			3'b010: result = operand_1 & operand_2;
+			3'b011: result = operand_1 | operand_2;
+			3'b101: result = ($signed(operand_1) < $signed(operand_2)) ? 32'd1 : 32'd0;
+			default: result = 32'd0;
+		endcase
+	end
+
+	always_comb begin
+		z = (result == 32'd0);
+		n = result[31];
+		c = (alu_ctrl == 3'b000) ? (operand_1 + operand_2) > 32'hFFFFFFFF : (alu_ctrl == 3'b001) ? (operand_1 < operand_2) : 1'b0;
+
+		case (alu_ctrl)
+			3'b000: v = (~operand_1[31] & ~operand_2[31] & result[31]) | (operand_1[31] & operand_2[31] & ~result[31]);
+			3'b001: v = (~operand_1[31] & operand_2[31] & result[31]) | (operand_1[31] & ~operand_2[31] & ~result[31]);
+			default: v = 1'b0;
+		endcase
+
+		flags = {n, z, c, v};
+	end
+
+endmodule

lab6/alu_task_tb.sv

@@ -0,0 +1,56 @@
+`timescale 1ns/1ps
+
+module alu_task_tb;
+    logic [31:0] operand_1, operand_2;
+    logic [2:0]  alu_ctrl;
+    logic [31:0] result;
+    logic [3:0]  flags;
+
+    alu_task DUT (
+        .operand_1(operand_1),
+        .operand_2(operand_2),
+        .alu_ctrl(alu_ctrl),
+        .result(result),
+        .flags(flags)
+    );
+
+    initial begin
+        operand_1 = 32'd10;
+        operand_2 = 32'd5;
+        alu_ctrl = 3'b000;
+        #10;
+
+        operand_1 = 32'd10;
+        operand_2 = 32'd20;
+        alu_ctrl = 3'b001;
+        #10;
+
+        operand_1 = 32'hFF00FF00;
+        operand_2 = 32'h0F0F0F0F;
+        alu_ctrl = 3'b010;
+        #10;
+
+        operand_1 = 32'hFF00FF00;
+        operand_2 = 32'h0F0F0F0F;
+        alu_ctrl = 3'b011;
+        #10;
+
+        operand_1 = -32'sd5;
+        operand_2 = 32'sd3;
+        alu_ctrl = 3'b101;
+        #10;
+
+        operand_1 = 32'sd10;
+        operand_2 = -32'sd3;
+        alu_ctrl = 3'b101;
+        #10;
+
+        operand_1 = 32'd5;
+        operand_2 = -32'd5;
+        alu_ctrl = 3'b000;
+        #10;
+
+        $stop;
+    end
+
+endmodule

lab6/u_4_divider.sv

@@ -0,0 +1,24 @@
+module u_4_divider(
+	input logic [3:0] operand_1, operand_2,
+	output logic [3:0] q, r
+	);
+
+	logic [4:0] part_r, d;
+
+	always_comb begin
+		q = 4'd0;
+		part_r = 5'd0;
+
+		for (int i = 3; i >= 0; i--) begin
+			part_r = {part_r[3:0], operand_1[i]};
+			d = part_r - {1'b0, operand_2};
+			if (d[4]) q[i] = 1'b0;
+			else begin
+				q[i] = 1'b1;
+				part_r = d;
+			end
+		end
+		r = part_r[3:0];
+	end
+
+endmodule

lab6/u_4_divider_tb.sv

@@ -0,0 +1,25 @@
+`timescale 1ns/1ps
+
+module u_4_divider_tb;
+
+	logic [3:0] operand_1, operand_2;
+	logic [3:0] q, r;
+
+	u_4_divider DUT (
+		.operand_1(operand_1),
+		.operand_2(operand_2),
+		.q(q),
+		.r(r)
+		);
+
+	initial begin
+		operand_1 = 4'b0110; operand_2 = 4'b0011;
+		#10;
+		operand_1 = 4'b0111; operand_2 = 4'b0111;
+		#10;
+		operand_1 = 4'b0111; operand_2 = 4'b0101;
+		#10;
+		$stop;
+	end
+
+endmodule