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1. Power-Reduction-in-Half-Subtractor-by-Gate-Sizing-Techniques Power-Reduction-in-Half-Subtractor-by-Gate-Sizing-Techniques Public

   Performed power analysis of a half subtractor circuit using parametric analysis for 180nm technology with Cadence Virtuoso

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2. Synthesizable-Parametrized-ALU-Design Synthesizable-Parametrized-ALU-Design Public

   Arithmetic and logical units are an integral part of any SOC that performs Arithmetic and logical operations. The ALU designed in this project supports variety of functions including arithmetic ope…

   Verilog 1

3. Universal-Shift-Register-and-Johnson-Counter Universal-Shift-Register-and-Johnson-Counter Public

   The register and counter circuit are simulated and designed using four 4:1 MUX which is used to select the operations (like SISO, PISO, PIPO, SIPO), IC555 timer is used to give clock pulse and D fl…

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4. Verilog-Based-Verification-of-a-MOD-10-Counter-Design Verilog-Based-Verification-of-a-MOD-10-Counter-Design Public

   The MOD-10 counter was functionally verified using a Verilog testbench to validate reset, load, increment, and rollover operations. Out of 2987 executed test cases, 2937 passed successfully, achiev…

   Verilog 1

5. Understanding_Python Understanding_Python Public

   This repository is my Python learning journey through the freeCodeCamp Python course (https://www.freecodecamp.org/learn/python-v9/ ). It includes hands-on projects and practical exercises related …

   Python 1

6. RAM_Verification RAM_Verification Public

   A 1024x8 synchronous RAM was verified using directed tests with task-based stimulus for better code density. Line coverage reached 100%, but toggle coverage is ~50–57%, showing limited signal activ…

   Verilog 1