This repository presents the obfuscation results which are generated by our custom tool TOTe (Tuneable Design Obfuscation Technique using eASIC). This tool is developed in the Centre for Hardware Security, Tallinn University of Technology (TalTech), Estonia to prevent the numerous security threats associated with CAD design flow. The repository consists of RTL, constraints and reports for the paper accepted in Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Shanghai, P.R. China, December 16-18, 2021. The constraints files consist of force logic for actual timing analysis. Moreover, it also represents the bitstream of the obfuscated circuit. Obfuscation criteria are user-defined parameters to obfuscate the design intent and it generates the timing reports in three different formats (alphanumeric, cleaned timing report before and after obfuscation).
The published paper is available on IEEEexplore with the following name: From FPGAs to Obfuscated eASICs: Design and SecurityTrade-offs
Use the following format of your choice to cite this paper:
1- Bibtex
@INPROCEEDINGS{eASIC,
author={Abideen, Zain Ul and Perez, Tiago Diadami and Pagliarini, Samuel},
booktitle={2021 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)},
title={From FPGAs to Obfuscated eASICs: Design and Security Trade-offs},
year={2021},
volume={},
number={},
pages={1-4},
doi={10.1109/AsianHOST53231.2021.9699758}
}
2- IEEE
Z. U. Abideen, T. D. Perez and S. Pagliarini, "From FPGAs to Obfuscated eASICs: Design and Security Trade-offs," 2021 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 2021, pp. 1-4, doi: 10.1109/AsianHOST53231.2021.9699758.
3- Preprint
The preprint of the paper is available on the following link: https://arxiv.org/abs/2110.05335