Generate design-rule matrix from per-fab TOML source of truth - #32
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Scopes the move from hand-maintained .kicad_dru files to files generated from a per-fab TOML source of truth: architecture, schema, the focused variant matrix, impedance-controlled net classes (with the stackup-dependency caveat), full replacement of legacy files, and CI regeneration checks.
Replaces the hand-maintained JLCPCB.kicad_dru / PCBWay.kicad_dru (with their error-prone 'Choose between' comment blocks) with concrete files generated per build variant from capabilities/<FAB>.toml by tools/generate_dru.py. - capabilities/JLCPCB.toml, capabilities/PCBWay.toml: values + variants + flags, seeded from the previous committed rules. - tools/generate_dru.py: emits one .kicad_dru per variant (default variant keeps the plain <FAB>.kicad_dru name); --check fails if committed output drifts. - Generated matrix: 2L-1oz, 4L-1oz (default), 4L-2oz, 6L-1oz per fab. - Every file gains impedance-controlled net classes (50R, 60R/90R/100R/120R_Diff) with typical starting values and a stackup-dependency warning. - JLCPCB gains the NPTH-to-Copper (non-Track) rule, which #31's message listed but never actually landed in the file. - lint_dru.py: derive the fab prefix from the part before the first '-'. - CI: run the generator --check before linting. Generated defaults are rule-for-rule equivalent to the previous files (bar the removed comment alternates and the additive net-class/NPTH-copper rules).
…t classes - Explain files are generated from capabilities/<FAB>.toml; edit the TOML, not the output. - Add a variant-selection table (2L/4L/4L-2oz/6L) for choosing a file. - Document the 50R / 60R/90R/100R/120R_Diff net classes and the stackup caveat. - Update the Validation section for the in-sync + lint CI checks.
tools/gen_comparison.py reads the same capabilities/*.toml source and emits a side-by-side of every fab's rule values: fixed limits at the default variant, per-variant trace/via/drill values, impedance net classes, and process-flag differences. Wired into CI with a --check in-sync gate and linked from README.
Addresses review findings on the generator overhaul: - generate_dru.py: add validate() that fails early with clear messages on a bad default_variant, empty/duplicate variants, a flag set without its backing constant (e.g. emit_bga without bga_to_trace), or a differential net class missing its gap. Enrich the missing-value error with fab/variant context. - generate_dru.py: --check now flags orphaned .kicad_dru files (left after a variant rename/removal) and generation prunes them, so CI can't stay green while a stale rule file ships. - gen_comparison.py: validate() each fab too, so the comparison can't be built against a silently-wrong default variant. - lint_dru.py: derive the fab prefix from the rules themselves and check the filename starts with it — correct for hyphenated fab names and variant files, instead of naively splitting the filename on '-'. - tools/test_tools.py: dependency-free test suite (linter negative cases, validate() rejections, generated-output round-trip) wired into CI.
The plainly-named <FAB>.kicad_dru is the 4L-1oz variant for both fabs; a header note now names the current variant and lists the others so a user whose order differs (e.g. a 2-layer board opening the default file) is steered to the right one instead of silently getting looser 4-layer minimums.
.github/workflows/drc.yml installs KiCad and runs 'kicad-cli pcb drc' against each fab's default board with its generated .kicad_dru, on manual dispatch and on board/rule changes. It publishes a JSON report artifact and a job summary. Deliberately non-gating (no --exit-code-violations): the test boards contain intentional pass/fail footprints, so violations are expected. Rule-file syntax stays gated by lint.yml. README Validation section updated.
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Heads up: this branch carries the bug from #33 into all eight generated files. The generator hard-codes Those are Board Setup display names. A Fix is pushed to Merge that branch in, or cherry-pick Refs #33 |
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Re-homed. This work now lives at Cimos/kicad-druid#1, merged up to the new repo's Lint and the tool tests pass there. This PR can be closed; the branch stays put for reference. |
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Superseded and now landed: this work was re-homed as kicad-druid#1, reviewed, hardened (TOML validation, repo-wide orphan detection, 108 tests) and merged there today. Closing. |
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The overhaul we scoped: move from hand-maintained
.kicad_drufiles to files generated from a single source of truth per fab. SeeDESIGN.mdfor the full rationale.What changed
capabilities/JLCPCB.toml,capabilities/PCBWay.toml— every value + fab metadata + variant overrides + feature flags, seeded from the previously committed rules (no value changes to the standard variant).tools/generate_dru.py(dependency-free, stdlibtomllib) emits one.kicad_druper variant. The default variant keeps the plain<FAB>.kicad_druname; others get<FAB>-<id>.kicad_dru.--checkfails if committed output drifts from the TOML.2L-1oz,4L-1oz(default),4L-2oz,6L-1oz.50R(single-ended) and60R_Diff/90R_Diff/100R_Diff/120R_Diff. Values are typical starting points for each fab's default stackup, using(opt …)so they guide the router without nuisance DRC errors, with a loud stackup-dependency warning in-file and in the README.generate_dru.py --check(in-sync) beforelint_dru.py.Behaviour vs today
The generated default files are rule-for-rule equivalent to the previous hand-maintained files, except:
NPTH to Copper (non-Track)— Add CI linting, JLCPCB rule parity, and KiCad version/docs refresh #31's commit message listed this rule but it never actually landed in the file (PCBWay got it in #13 Refactor PCBWay rules to mirror JLCPCB structure #29). The generator emits it for both fabs now, closing that gap.Follow-ups (not in this PR)
kicad-cli pcb drcgolden tests; widen the variant matrix.Every generated file passes both the linter and the in-sync check.
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