Verilog Generator & Smart FSM Editor
A web-based tool combining natural language Verilog generation with visual FSM editing for rapid prototyping and verification of digital logic designs.
RTL Copilot helps embedded hardware developers and FPGA engineers:
- Generate Verilog from natural language — Describe what you want, get syntactically correct RTL
- Visually design FSMs — Drag-and-drop state machine editor with automatic code generation
- Catch bugs early — Detect common RTL issues before simulation
- Integrate with your workflow — Export to standard formats for existing EDA toolchains
Describe your hardware in plain English. RTL Copilot generates clean, synthesizable Verilog with proper coding conventions.
Design state machines graphically with ReactFlow-based canvas. Real-time bidirectional sync between visual editor and code.
Lint rules catch common mistakes:
- Undriven/unread signals
- Combinational loops
- Blocking vs non-blocking assignment issues
- Clock domain crossing warnings
Run testbenches with integrated iverilog/verilator backend. View results with in-browser waveform viewer.
| Layer | Technology |
|---|---|
| Frontend | Next.js 14, React, TypeScript |
| State | Zustand |
| FSM Canvas | ReactFlow |
| Code Editor | Monaco Editor |
| Visualization | D3.js |
| Styling | Tailwind CSS |
| LLM | Anthropic Claude API |
| Database | PostgreSQL + Redis |
| Simulation | iverilog / verilator (Docker) |
- Node.js 18+
- PostgreSQL 15+
- Redis
- Docker Desktop (for simulation)
- Anthropic API key
# Clone the repository
git clone https://github.com/cirkitly/rtl-copilot-plugin.git
cd rtl-copilot-plugin
# Install dependencies
npm install
# Set up environment
cp .env.example .env.local
# Edit .env.local with your credentials
# Run database migrations
npm run db:migrate
# Start development server
npm run devDATABASE_URL=postgresql://user:pass@localhost:5432/rtl_copilot
REDIS_URL=redis://localhost:6379
ANTHROPIC_API_KEY=sk-ant-xxx
NEXTAUTH_SECRET=your-secret
NEXTAUTH_URL=http://localhost:3000| Document | Description |
|---|---|
| Proposal | Full project proposal with architecture details |
| Implementation Plan | Technical implementation guide |
| Task Breakdown | Development checklist (24 weeks) |
Phase: Planning
Timeline: 24 weeks (6 months)
| Phase | Weeks | Status |
|---|---|---|
| 1. Foundation | 1-3 | ✅ Completed |
| 2. Verilog Core | 4-7 | ✅ Completed |
| 3. FSM Editor | 8-11 | ✅ Completed |
| 4. LLM Integration | 12-15 | 🔲 Not Started |
| 5. Code Editor & UI | 16-18 | 🔲 Not Started |
| 6. Simulation | 19-21 | 🔲 Not Started |
| 7. Polish & Deploy | 22-24 | 🔲 Not Started |
┌─────────────────────────────────────────────────────────────┐
│ Frontend (Next.js) │
├─────────────────────────────┬───────────────────────────────┤
│ FSM Visual Editor │ Monaco Code Editor │
│ (ReactFlow) │ (Verilog syntax) │
├─────────────────────────────┴───────────────────────────────┤
│ Prompt Input Bar │
├─────────────────────────────┬───────────────────────────────┤
│ Validation Results │ Simulation Waveforms │
└─────────────────────────────┴───────────────────────────────┘
│
▼
┌─────────────────────────────────────────────────────────────┐
│ Backend (Next.js API) │
├─────────────────────────────────────────────────────────────┤
│ Verilog Parser │ FSM Engine │ LLM Client │ Validator │
└─────────────────────────────────────────────────────────────┘
│
┌───────────────┼───────────────┐
▼ ▼ ▼
PostgreSQL Redis Docker
(projects) (cache) (simulation)
Contributions are welcome! Please read the implementation plan before getting started.
- Fork the repository
- Create your feature branch (
git checkout -b feature/amazing-feature) - Commit your changes (
git commit -m 'Add amazing feature') - Push to the branch (
git push origin feature/amazing-feature) - Open a Pull Request
MIT License. See LICENSE for details.
Built for hardware engineers who want to move fast.