Lightweight Streaming Spiking Neural Network Components

A flexible and modular hardware framework for building custom Spiking Neural Network (SNN) accelerators for FPGAs and ASICs.

This repository provides highly customizable hardware components with standard AXI-Stream interfaces. These blocks can be chained and interconnected in an arbitrary fashion to generate highly optimized, application-specific SNN architectures.

Link to publication follows soon.

Proven Use Cases

This framework has been successfully utilized to design, generate, and synthesize highly efficient SNN accelerators for several standard neuromorphic datasets:

• PSMNIST (Permuted Spiking MNIST)
• SSC (Spiking Speech Commands)
• SHD (Spiking Heidelberg Digits)

SHD Accelerator Architecture

To demonstrate the framework's capabilities, below is the block diagram of the custom accelerator architecture generated specifically for the Spiking Heidelberg Digits (SHD) dataset.

Hardware Components

The framework is built around a library of modular, AXI-Stream compatible hardware blocks. Currently, the following core components are implemented and available in the rtl/ directory:

Fully Connected Layer: Implements a straightforward linear layer followed by a spiking activation step. The default activation function is a Leaky Integrate-and-Fire (LIF) neuron, but the modular architecture allows this to be easily swapped out for other custom neuron models.

Recurrent Path Block: Enables the routing of recurrent connections, allowing you to build Recurrent Spiking Neural Networks (RSNNs) by feeding data back into fully connected layers.

Delay Block: Introduces configurable axonal delays into the network. This block can be inserted into both the feedforward and recurrent paths to implement complex temporal dynamics within your accelerator.

Repository Structure

• rtl/: Contains the core hardware components provided as VHDL source files. These modular blocks communicate via AXI-Stream and form the building blocks of the neural network layers.
• configs/: Contains JSON configuration files. These files define the high-level architecture of your specific accelerator (e.g., number of layers, neuron parameters, and network topology).
• python/: Contains Python utilities, most notably network_conf_generator.py, which bridges the software configuration with the hardware implementation.

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How It Works

Building a custom accelerator with this framework requires three main steps: Configure, Generate, and Synthesize.

1. Configure the Network

Define your Spiking Neural Network architecture by creating or modifying a JSON file in the configs/ directory. You can specify the number of layers, interconnection properties, and specific hardware parameters for the SNN.

2. Generate the VHDL Package

Use the provided Python script to parse your JSON configuration and automatically generate a VHDL package containing the constants and configurations required by the RTL.

# Example usage of the configuration generator
python3 python/network_conf_generator.py -o generated_rtl/shd_network_pkg.vhd configs/shd_conf.json

3. Synthesize

Once the VHDL package is generated, combine it with the VHDL files located in the rtl/ directory. You can now load these files into your preferred EDA tool (e.g., Vivado, Quartus, Yosys) to synthesize, place, and route the final accelerator for your target FPGA or ASIC platform.

️ Dependencies

• Python 3.x: Required to run the network_conf_generator.py script.
• EDA Tool: A VHDL-93 compatible synthesis tool (e.g., Xilinx Vivado, Altera Quartus Prime, Yosys, ...). A copy of the IEEE fixed_pkg adjusted for use with VHDL-93 has been provided in the rtl/ directory, which needs to be synthesized into the ieee_proposed library.