Pinned Loading
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16-bit-RISC-Processor
16-bit-RISC-Processor PublicCustom 16-bit multi-cycle RISC processor using Verilog HDL
Verilog
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Design-and-Synthesis-of-Majority-Logic-Gate-Based-MAC-Units
Design-and-Synthesis-of-Majority-Logic-Gate-Based-MAC-Units PublicDesign and Synthesis of Majority Logic Gate Based MAC Units with FPGA and ASIC Evaluation
Verilog
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FPGA-Based-Spiking-Neural-Network-MNIST
FPGA-Based-Spiking-Neural-Network-MNIST PublicFPGA-based Spiking Neural Network (SNN) accelerator for MNIST digit recognition using Verilog HDL, LIF neurons, STDP learning and Winner-Take-All competition.
Verilog 1
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Sequence-Detector-Verilog
Sequence-Detector-Verilog PublicSequence Detector using Moore and Mealy FSMs in Verilog HDL with overlapping and non-overlapping detection schemes.
Verilog
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Traffic-Light-Controller-Verilog
Traffic-Light-Controller-Verilog PublicTraffic Light Controller for a Four-Way Intersection using Verilog HDL with vehicle detection and counter-based signal timing.
Verilog
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Vending-Machine-Controller-Verilog
Vending-Machine-Controller-Verilog PublicFSM-based Vending Machine Controller using Verilog HDL with support for coin payments, online payments, change return, and product dispensing.
Verilog
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