Add RISC-V vector spec v1.0 support (new submission)

.gitignore

@@ -29,6 +29,7 @@ rdft/simd/neon/*.c
 rdft/simd/sse2/*.c
 rdft/simd/sve*/*.c
 rdft/simd/vsx/*.c
+rdft/simd/rvv*/*.c
 rdft/scalar/r2cb/*.c
 rdft/scalar/r2cf/*.c
 rdft/scalar/r2r/*.c
@@ -48,6 +49,7 @@ dft/simd/neon/*.c
 dft/simd/sse2/*.c
 dft/simd/sve*/*.c
 dft/simd/vsx/*.c
+dft/simd/rvv*/*.c
 
 # other generated files
 ChangeLog

Makefile.am

@@ -118,6 +118,29 @@ LASX_LIBS = dft/simd/lasx/libdft_lasx_codelets.la  \
 rdft/simd/lasx/librdft_lasx_codelets.la
 endif
 
+if HAVE_RVV
+RVV_LIBS = dft/simd/rvv128/libdft_rvv128_codelets.la      \
+rdft/simd/rvv128/librdft_rvv128_codelets.la	\
+dft/simd/rvv256/libdft_rvv256_codelets.la      \
+rdft/simd/rvv256/librdft_rvv256_codelets.la	\
+dft/simd/rvv512/libdft_rvv512_codelets.la      \
+rdft/simd/rvv512/librdft_rvv512_codelets.la	\
+dft/simd/rvv1024/libdft_rvv1024_codelets.la      \
+rdft/simd/rvv1024/librdft_rvv1024_codelets.la      \
+dft/simd/rvv2048/libdft_rvv2048_codelets.la      \
+rdft/simd/rvv2048/librdft_rvv2048_codelets.la      \
+dft/simd/rvv4096/libdft_rvv4096_codelets.la      \
+rdft/simd/rvv4096/librdft_rvv4096_codelets.la      \
+dft/simd/rvv8192/libdft_rvv8192_codelets.la      \
+rdft/simd/rvv8192/librdft_rvv8192_codelets.la      \
+dft/simd/rvv16384/libdft_rvv16384_codelets.la      \
+rdft/simd/rvv16384/librdft_rvv16384_codelets.la    \
+dft/simd/rvv32768/libdft_rvv32768_codelets.la      \
+rdft/simd/rvv32768/librdft_rvv32768_codelets.la    \
+dft/simd/rvv65536/libdft_rvv65536_codelets.la      \
+rdft/simd/rvv65536/librdft_rvv65536_codelets.la
+endif
+
 if HAVE_GENERIC_SIMD128
 GENERIC_SIMD128_LIBS = dft/simd/generic-simd128/libdft_generic_simd128_codelets.la \
 rdft/simd/generic-simd128/librdft_generic_simd128_codelets.la
@@ -151,7 +174,7 @@ libfftw3@PREC_SUFFIX@_la_LIBADD =			\
         $(SIMD_LIBS) $(SSE2_LIBS) $(AVX_LIBS) $(AVX_128_FMA_LIBS) \
         $(AVX2_LIBS) $(ALTIVEC_LIBS) \
         $(VSX_LIBS) $(NEON_LIBS) $(SVE_LIBS) $(KCVI_LIBS) $(AVX512_LIBS) \
-        $(LSX_LIBS) $(LASX_LIBS) \
+        $(LSX_LIBS) $(LASX_LIBS) $(RVV_LIBS) \
         $(GENERIC_SIMD128_LIBS) $(GENERIC_SIMD256_LIBS) \
 	$(COMBINED_THREADLIBS)
 

api/version.c

@@ -89,6 +89,10 @@ const char X(version)[] = PACKAGE "-" PACKAGE_VERSION
    "-mlasx"
 #endif
 
+#if HAVE_RVV
+   "-rvv"
+#endif
+
 #if defined(HAVE_GENERIC_SIMD128)
    "-generic_simd128"
 #endif

cmake.config.h.in

@@ -202,6 +202,9 @@
 /* Define to enable ARM NEON optimizations. */
 /* #undef HAVE_NEON */
 
+/* Define to enable RISC-V Vector optimizations. */
+/* #undef HAVE_RVV */
+
 /* Define if OpenMP is enabled */
 #cmakedefine HAVE_OPENMP
 

configure.ac

@@ -254,6 +254,12 @@ if test "$have_sve" = "yes"; then
 fi
 AM_CONDITIONAL(HAVE_SVE, test "$have_sve" = "yes")
 
+AC_ARG_ENABLE(rvv, [AC_HELP_STRING([--enable-rvv],[enable RISC-V V optimizations])], have_rvv=$enableval, have_rvv=no)
+if test "$have_rvv" = "yes"; then
+        AC_DEFINE(HAVE_RVV,1,[Define to enable RISC-V V optimizations.])
+fi
+AM_CONDITIONAL(HAVE_RVV, test "$have_rvv" = "yes")
+
 dnl FIXME:
 dnl AC_ARG_ENABLE(mips-ps, [AS_HELP_STRING([--enable-mips-ps],[enable MIPS pair-single optimizations])], have_mips_ps=$enableval, have_mips_ps=no)
 dnl if test "$have_mips_ps" = "yes"; then
@@ -446,6 +452,12 @@ case "${ax_cv_c_compiler_vendor}" in
             AX_CHECK_COMPILE_FLAG(-mlasx, [LASX_CFLAGS="-mlasx"],
             [AC_MSG_ERROR([Need a version of gcc with -mlasx])])
         fi
+
+        # RVV
+        if test "$have_rvv" = "yes" -a "x$RVV_CFLAGS" = x; then
+            AX_CHECK_COMPILE_FLAG(-march=rv64gcv, [RVV_CFLAGS="-march=rv64gcv"],
+            [AC_MSG_ERROR([Need a version of gcc with -march=rv64gcv])])
+        fi
     ;;
 
     clang)
@@ -486,6 +498,12 @@ case "${ax_cv_c_compiler_vendor}" in
             AX_CHECK_COMPILE_FLAG(-mlasx, [LASX_CFLAGS="-mlasx"],
             [AC_MSG_ERROR([Need a version of clang with -mlasx])])
         fi
+
+        # RVV
+        if test "$have_rvv" = "yes" -a "x$RVV_CFLAGS" = x; then
+            AX_CHECK_COMPILE_FLAG(-march=rv64gcv, [RVV_CFLAGS="-march=rv64gcv"],
+            [AC_MSG_ERROR([Need a version of clang with -march=rv64gcv])])
+        fi
 
         case "${host_cpu}" in
             aarch64)
@@ -523,6 +541,7 @@ AC_SUBST(NEON_CFLAGS)
 AC_SUBST(SVE_CFLAGS)
 AC_SUBST(LSX_CFLAGS)
 AC_SUBST(LASX_CFLAGS)
+AC_SUBST(RVV_CFLAGS)
 
 dnl add stack alignment CFLAGS if so requested
 if test "$with_incoming_stack_boundary"x != "no"x; then
@@ -823,6 +842,16 @@ AC_CONFIG_FILES([
    dft/simd/sve2048/Makefile
    dft/simd/lsx/Makefile
    dft/simd/lasx/Makefile
+   dft/simd/rvv128/Makefile
+   dft/simd/rvv256/Makefile
+   dft/simd/rvv512/Makefile
+   dft/simd/rvv1024/Makefile
+   dft/simd/rvv2048/Makefile
+   dft/simd/rvv4096/Makefile
+   dft/simd/rvv8192/Makefile
+   dft/simd/rvv16384/Makefile
+   dft/simd/rvv32768/Makefile
+   dft/simd/rvv65536/Makefile
    dft/simd/generic-simd128/Makefile
    dft/simd/generic-simd256/Makefile
 
@@ -850,6 +879,16 @@ AC_CONFIG_FILES([
    rdft/simd/sve2048/Makefile
    rdft/simd/lsx/Makefile
    rdft/simd/lasx/Makefile
+   rdft/simd/rvv128/Makefile
+   rdft/simd/rvv256/Makefile
+   rdft/simd/rvv512/Makefile
+   rdft/simd/rvv1024/Makefile
+   rdft/simd/rvv2048/Makefile
+   rdft/simd/rvv4096/Makefile
+   rdft/simd/rvv8192/Makefile
+   rdft/simd/rvv16384/Makefile
+   rdft/simd/rvv32768/Makefile
+   rdft/simd/rvv65536/Makefile
    rdft/simd/generic-simd128/Makefile
    rdft/simd/generic-simd256/Makefile
 

dft/codelet-dft.h

@@ -113,6 +113,16 @@ extern const solvtab X(solvtab_dft_sve1024);
 extern const solvtab X(solvtab_dft_sve2048);
 extern const solvtab X(solvtab_dft_lsx);
 extern const solvtab X(solvtab_dft_lasx);
+extern const solvtab X(solvtab_dft_rvv128);
+extern const solvtab X(solvtab_dft_rvv256);
+extern const solvtab X(solvtab_dft_rvv512);
+extern const solvtab X(solvtab_dft_rvv1024);
+extern const solvtab X(solvtab_dft_rvv2048);
+extern const solvtab X(solvtab_dft_rvv4096);
+extern const solvtab X(solvtab_dft_rvv8192);
+extern const solvtab X(solvtab_dft_rvv16384);
+extern const solvtab X(solvtab_dft_rvv32768);
+extern const solvtab X(solvtab_dft_rvv65536);
 extern const solvtab X(solvtab_dft_generic_simd128);
 extern const solvtab X(solvtab_dft_generic_simd256);
 

dft/conf.c

@@ -99,6 +99,28 @@ void X(dft_conf_standard)(planner *p)
      if (X(have_simd_lasx)())
      X(solvtab_exec)(X(solvtab_dft_lasx), p);
 #endif
+#if HAVE_RVV
+     if (X(have_simd_rvv)(128))
+          X(solvtab_exec)(X(solvtab_dft_rvv128), p);
+     if (X(have_simd_rvv)(256))
+          X(solvtab_exec)(X(solvtab_dft_rvv256), p);
+     if (X(have_simd_rvv)(512))
+          X(solvtab_exec)(X(solvtab_dft_rvv512), p);
+     if (X(have_simd_rvv)(1024))
+          X(solvtab_exec)(X(solvtab_dft_rvv1024), p);
+     if (X(have_simd_rvv)(2048))
+          X(solvtab_exec)(X(solvtab_dft_rvv2048), p);
+     if (X(have_simd_rvv)(4096))
+          X(solvtab_exec)(X(solvtab_dft_rvv4096), p);
+     if (X(have_simd_rvv)(8192))
+          X(solvtab_exec)(X(solvtab_dft_rvv8192), p);
+     if (X(have_simd_rvv)(16384))
+          X(solvtab_exec)(X(solvtab_dft_rvv16384), p);
+     if (X(have_simd_rvv)(32768))
+          X(solvtab_exec)(X(solvtab_dft_rvv32768), p);
+     if (X(have_simd_rvv)(65536))
+          X(solvtab_exec)(X(solvtab_dft_rvv65536), p);
+#endif
 #if HAVE_GENERIC_SIMD128
      X(solvtab_exec)(X(solvtab_dft_generic_simd128), p);
 #endif

dft/simd/Makefile.am

@@ -1,4 +1,4 @@
 AM_CPPFLAGS = -I $(top_srcdir)
-SUBDIRS = common sse2 avx avx-128-fma avx2 avx2-128 avx512 kcvi altivec vsx neon sve128 sve256 sve512 sve1024 sve2048 lsx lasx generic-simd128 generic-simd256
+SUBDIRS = common sse2 avx avx-128-fma avx2 avx2-128 avx512 kcvi altivec vsx neon sve128 sve256 sve512 sve1024 sve2048 lsx lasx rvv128 rvv256 rvv512 rvv1024 rvv2048 rvv4096 rvv8192 rvv16384 rvv32768 rvv65536 generic-simd128 generic-simd256
 EXTRA_DIST = n1b.h n1f.h n2b.h n2f.h n2s.h q1b.h q1f.h t1b.h t1bu.h	\
 t1f.h t1fu.h t2b.h t2f.h t3b.h t3f.h ts.h codlist.mk simd.mk

dft/simd/rvv1024/Makefile.am

@@ -0,0 +1,13 @@
+AM_CFLAGS = $(RVV_CFLAGS)
+SIMD_HEADER=simd-support/simd-rvv1024.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv1024_codelets.la
+libdft_rvv1024_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

dft/simd/rvv128/Makefile.am

@@ -0,0 +1,13 @@
+AM_CFLAGS = $(RVV_CFLAGS)
+SIMD_HEADER=simd-support/simd-rvv128.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv128_codelets.la
+libdft_rvv128_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

dft/simd/rvv16384/Makefile.am

@@ -0,0 +1,13 @@
+AM_CFLAGS = $(RVV_CFLAGS)
+SIMD_HEADER=simd-support/simd-rvv16384.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv16384_codelets.la
+libdft_rvv16384_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

dft/simd/rvv2048/Makefile.am

@@ -0,0 +1,13 @@
+AM_CFLAGS = $(RVV_CFLAGS)
+SIMD_HEADER=simd-support/simd-rvv2048.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv2048_codelets.la
+libdft_rvv2048_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

dft/simd/rvv256/Makefile.am

@@ -0,0 +1,13 @@
+AM_CFLAGS = $(RVV_CFLAGS)
+SIMD_HEADER=simd-support/simd-rvv256.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv256_codelets.la
+libdft_rvv256_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

dft/simd/rvv32768/Makefile.am

@@ -0,0 +1,13 @@
+AM_CFLAGS = $(RVV_CFLAGS)
+SIMD_HEADER=simd-support/simd-rvv32768.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv32768_codelets.la
+libdft_rvv32768_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

dft/simd/rvv4096/Makefile.am

@@ -0,0 +1,13 @@
+AM_CFLAGS = $(RVV_CFLAGS)
+SIMD_HEADER=simd-support/simd-rvv4096.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv4096_codelets.la
+libdft_rvv4096_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

dft/simd/rvv512/Makefile.am

@@ -0,0 +1,13 @@
+AM_CFLAGS = $(RVV_CFLAGS)
+SIMD_HEADER=simd-support/simd-rvv512.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv512_codelets.la
+libdft_rvv512_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

dft/simd/rvv65536/Makefile.am

@@ -0,0 +1,13 @@
+AM_CFLAGS = $(RVV_CFLAGS)
+SIMD_HEADER=simd-support/simd-rvv65536.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv65536_codelets.la
+libdft_rvv65536_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

dft/simd/rvv8192/Makefile.am

@@ -0,0 +1,13 @@
+AM_CFLAGS = $(RVV_CFLAGS)
+SIMD_HEADER=simd-support/simd-rvv8192.h
+
+include $(top_srcdir)/dft/simd/codlist.mk
+include $(top_srcdir)/dft/simd/simd.mk
+
+if HAVE_RVV
+
+BUILT_SOURCES = $(EXTRA_DIST)
+noinst_LTLIBRARIES = libdft_rvv8192_codelets.la
+libdft_rvv8192_codelets_la_SOURCES = $(BUILT_SOURCES)
+
+endif

doc/install.texi

@@ -199,6 +199,7 @@ of the time).  @xref{Cycle Counters}.
 @code{--enable-altivec} (single),
 @code{--enable-vsx} (single, double),
 @code{--enable-neon} (single, double on aarch64),
+@code{--enable-rvv} (single, double on risc-v vector),
 @code{--enable-generic-simd128},
 and
 @code{--enable-generic-simd256}:

doc/intro.texi

@@ -18,7 +18,7 @@ transform (DFT) and various special cases thereof.
 
 @item  FFTW supports arbitrary multi-dimensional data.
 
-@item  FFTW supports the SSE, SSE2, AVX, AVX2, AVX512, KCVI, Altivec, VSX, and
+@item  FFTW supports the SSE, SSE2, AVX, AVX2, AVX512, KCVI, Altivec, VSX, RISC-V V, and
        NEON vector instruction sets.
 
 @item  FFTW includes parallel (multi-threaded) transforms

doc/other.texi

@@ -16,7 +16,7 @@ special operations supported by some processors to perform a single
 operation on several numbers (usually 2 or 4) simultaneously.  SIMD
 floating-point instructions are available on several popular CPUs:
 SSE/SSE2/AVX/AVX2/AVX512/KCVI on some x86/x86-64 processors, AltiVec and
-VSX on some POWER/PowerPCs, NEON on some ARM models.  FFTW can be
+VSX on some POWER/PowerPCs, NEON on some ARM models, V extension on some RISC-V models.  FFTW can be
 compiled to support the SIMD instructions on any of these systems.
 @cindex SIMD
 @cindex SSE

kernel/ifftw.h

@@ -114,6 +114,7 @@ extern void X(extract_reim)(int sign, R *c, R **r, R **i);
     defined(HAVE_SSE2)||                        \
     defined(HAVE_SVE)||                         \
     defined(HAVE_VSX)||                         \
+    defined(HAVE_RVV)||                         \
     defined(HAVE_GENERIC_SIMD128) ||            \
     defined(HAVE_GENERIC_SIMD256)
 #define HAVE_SIMD 1
@@ -133,6 +134,7 @@ extern int X(have_simd_neon)(void);
 extern int X(have_simd_lsx)(void);
 extern int X(have_simd_lasx)(void);
 extern int X(have_simd_sve)(int minwidth);
+extern int X(have_simd_rvv)(int minwidth);
 
 /* forward declarations */
 typedef struct problem_s problem;
@@ -874,7 +876,7 @@ enum { TW_COS = 0, TW_SIN = 1, TW_CEXP = 2, TW_NEXT = 3,
 
 typedef struct {
      unsigned char op;
-     signed char v;
+     short v;
      short i;
 } tw_instr;