8-bit Shifter IC Design RTL2GDSII

This repository provides a complete guide and all necessary files for the VLSI design process of an 8-bit Shifter, from Register Transfer Level (RTL) development to Static Timing Analysis (STA). It's designed to showcase a practical, industry-standard flow for digital ASIC design.

🌟 Project Overview

The 8-bit-Shifter-RTL2GDSII project meticulously documents and implements the entire digital design flow for an 8-bit Shifter. This includes everything from writing the Verilog RTL code and verifying its functionality, through logic synthesis, physical design (place and route), and finally, performing comprehensive static timing analysis to ensure performance targets are met.

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✨ Key Features

• 8-bit Shifter Implementation: A practical and widely used digital circuit for demonstration.

• Detailed Design Stages:

  1. RTL Development & Verification: Verilog RTL code for the 8-bit shifter and testbench for functional verification.

  2. Logic Synthesis: Mapping RTL to a gate-level netlist using standard cell libraries.

  3. Physical Design: Floorplanning, power planning, cell placement, clock tree synthesis (CTS), and routing.

  4. Static Timing Analysis (STA): Comprehensive timing verification inclusive of RC parasitic corners to ensure design meets frequency targets.

• Scripted Flow: Includes TCL scripts for automating various stages of the design flow.

• Organized Structure: Well-defined directory structure for each design stage and related files.

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🚀 Technologies and Tools Used

This project leverages industry-standard Electronic Design Automation (EDA) tools by Synopsys Inc.:

• RTL Simulation & Verification Tools: VCS, Verdi

• Logic Synthesis Tool: Design Compiler (DC)

• Physical Design Tool: IC Compiler II (ICCII)

• Static Timing Analysis Tool: PrimeTime (PT)

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📁 Repository Structure

The repository is organized into the following key directories:

CONSTRAINTS/: Contains design constraints file (.sdc).

DC/: Files related to the Design Compiler (Logic Synthesis) stage i.e., TCL scripts for logic synthesis and setup; area, timing, and power reports and results of Logic Synthesis.

ICCII/: Files related to the IC Compiler II (Physical Design) stage i.e., TCL scripts for each Physical Design step; reports and results of Physical Design.

PT/: Files related to PrimeTime (Static Timing Analysis) i.e., TCL scripts for STA.

ref/: Reference files, such as standard cell libraries (.lib, .db), technology files (.tf), and parasitic information files (.tluplus).

rtl_simulation/: Verilog RTL code, testbench for functional verification, and simulation commands.

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⚙️ Installation and Setup

To replicate this design flow, you will need access to the specified Synopsys EDA tools and a Linux-based environment.

Clone the Repository:

git clone https://github.com/Free-95/8-bit-Shifter-RTL2GDSII.git
cd 8-bit-Shifter-RTL2GDSII

Environment Setup:

Ensure all required EDA tools (VCS, Verdi, Design Compiler, IC Compiler II, PrimeTime) are installed and properly licensed on your system.

Library Files:

Place your standard cell library files (e.g., .lib, .db, .ndm files for your chosen technology node) into the ref/ directory or update the paths in the provided TCL scripts to point to your library locations.

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💡 Usage

The design flow is managed through a series of TCL scripts, typically executed within the respective EDA tool environments.

1. RTL Development & Verification

   • Navigate to the rtl_simulation/ directory.

   • Execute the simulation commands provided in vcs_command file.

   • Verify the functional correctness of the 8-bit shifter using Verdi.

2. Logic Synthesis

   • Navigate to the DC/ directory.

   • Launch Synopsys Design Compiler Shell (dc_shell) and execute the synthesis TCL script run_dc.tcl.

   • The output will be a level-1 gate-level netlist (Verilog) and synthesis reports.

3. Physical Design

   • Navigate to the ICCII/ directory.

   • Launch Synopsys IC Compiler II Shell (icc2_shell) and execute the physical design TCL scripts in given sequence - floorplan.tcl, power_planning.tcl, placement.tcl, clock.tcl, and route.tcl.

   • The output will be a level-2 gate-level netlist and various physical design reports.

4. Static Timing Analysis

   • Navigate to the PT/ directory.

   • Launch Synopsys PrimeTime Shell (pt_shell) and execute the STA TCL scripts run_pt_p1.tcl (For Late Corner) and run_pt_p2.tcl (For Early Corner). This will perform comprehensive timing checks on the generated netlist, keeping Standard Parasitic Exchange Format files (.spef) in consideration.

   • The output will be detailed timing reports, crucial for verifying the design's performance.

NOTE: TCL Scripts contain relative paths, so execute them in dedicated directories or change paths according to your convenience.