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AI-powered FPGA development plugin for Claude Code with Verilog simulation and knowledge graph

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ChipForge Plugin

AI-powered FPGA development toolkit for Claude Code.

Features

  • Verilog Simulation: Syntax check, compile, and simulate using Icarus Verilog
  • Waveform Analysis: Convert VCD to WaveJSON for visualization
  • Knowledge Graph: Track signal relationships and design patterns
  • FPGA Workflow: Automated design → verify → document workflow

Requirements

  • Claude Code CLI installed
  • Windows (Linux/macOS support planned)

Installation

Copy the skill to your Claude Code skills directory:

# Windows (PowerShell)
Copy-Item -Recurse skills/chipforge $env:USERPROFILE\.claude\skills\

# Windows (Git Bash)
cp -r skills/chipforge ~/.claude/skills/

# Linux/macOS
cp -r skills/chipforge ~/.claude/skills/

Project Structure

chipforge-plugin/
├── skills/
│   └── chipforge/
│       ├── SKILL.md              # Skill definition
│       └── bin/
│           ├── iverilog/         # Icarus Verilog simulator
│           ├── vcd2wavedrom.exe  # VCD to WaveJSON converter
│           └── chipforge-kg.exe  # Knowledge graph CLI
└── tools/
    └── kg/                       # Go source for knowledge graph

Usage

After installation, use the /chipforge command in Claude Code:

Design a Verilog Module

/chipforge Design a PWM controller module:
- 8-bit duty cycle input (0-255)
- Interfaces: clk, rst_n, duty[7:0], pwm_out
- State machine: COUNT → COMPARE → OUTPUT

Check Verilog Syntax

/chipforge Check syntax for rtl/counter.v

Run Simulation

/chipforge Run simulation for my_project

Analyze Waveform

/chipforge Analyze waveform sim.vcd

Knowledge Graph Operations

/chipforge Create knowledge graph for spi_master project
/chipforge Add signal clk to spi_master graph
/chipforge Query relations for mosi signal

Workflow

The skill follows this FPGA development workflow:

[Init KG] → [Write Code] → [Syntax Check]
                               ↓
               [Fix Code] ← [Errors?]
                               ↓ No
                          [Compile]
                               ↓
               [Fix Code] ← [Errors?]
                               ↓ No
                          [Simulate]
                               ↓
                         [Analyze VCD]
                               ↓
               [Fix Code] ← [Issues?]
                               ↓ No
                        [Update KG] → [Done]

Building from Source

Knowledge Graph Tool

cd tools/kg
go build -o ../../bin/chipforge-kg.exe

License

MIT

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AI-powered FPGA development plugin for Claude Code with Verilog simulation and knowledge graph

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