AI-powered FPGA development toolkit for Claude Code.
- Verilog Simulation: Syntax check, compile, and simulate using Icarus Verilog
- Waveform Analysis: Convert VCD to WaveJSON for visualization
- Knowledge Graph: Track signal relationships and design patterns
- FPGA Workflow: Automated design → verify → document workflow
- Claude Code CLI installed
- Windows (Linux/macOS support planned)
Copy the skill to your Claude Code skills directory:
# Windows (PowerShell)
Copy-Item -Recurse skills/chipforge $env:USERPROFILE\.claude\skills\
# Windows (Git Bash)
cp -r skills/chipforge ~/.claude/skills/
# Linux/macOS
cp -r skills/chipforge ~/.claude/skills/chipforge-plugin/
├── skills/
│ └── chipforge/
│ ├── SKILL.md # Skill definition
│ └── bin/
│ ├── iverilog/ # Icarus Verilog simulator
│ ├── vcd2wavedrom.exe # VCD to WaveJSON converter
│ └── chipforge-kg.exe # Knowledge graph CLI
└── tools/
└── kg/ # Go source for knowledge graph
After installation, use the /chipforge command in Claude Code:
/chipforge Design a PWM controller module:
- 8-bit duty cycle input (0-255)
- Interfaces: clk, rst_n, duty[7:0], pwm_out
- State machine: COUNT → COMPARE → OUTPUT
/chipforge Check syntax for rtl/counter.v
/chipforge Run simulation for my_project
/chipforge Analyze waveform sim.vcd
/chipforge Create knowledge graph for spi_master project
/chipforge Add signal clk to spi_master graph
/chipforge Query relations for mosi signal
The skill follows this FPGA development workflow:
[Init KG] → [Write Code] → [Syntax Check]
↓
[Fix Code] ← [Errors?]
↓ No
[Compile]
↓
[Fix Code] ← [Errors?]
↓ No
[Simulate]
↓
[Analyze VCD]
↓
[Fix Code] ← [Issues?]
↓ No
[Update KG] → [Done]
cd tools/kg
go build -o ../../bin/chipforge-kg.exeMIT