LNA-45nm-Design

Designing of a Single Stage Low Noise Amplifier. Masters Project for EE 210: RFIC at San Jose State University

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
EE220		EE220
EE220_CID04_CID11_Low power LNA design in 45nm CMOS.pdf		EE220_CID04_CID11_Low power LNA design in 45nm CMOS.pdf
README.md		README.md

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