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Added some of the interfaces/ports as described in the one-pager for AXI Crossbar. Size and quantity of ports subject to change
Initial SV32 MMU module skeleton
Cache branch
DMA Controller: Initial subsystem implementation
Pull request template for consistent pull request format.
Majority of code implemented, still needs more work to fully integrate with bus
Initial timer interrupt logic implemented
Interrupts Module Briefs and PLIC
Initial AXI Module skeleton
Added FIFO Management code
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@ryanhansen640 Please reformat this pull request to merge with |
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Added FIFO Management code.
(New to Github so let me know if anything else needs to be done)