chore: track plans/ in repo and add INDEX

.gitignore

@@ -45,6 +45,5 @@ telemetry-*.zip
 # Private files and plans
 private/
 references/
-plans/
 .plans/
 tmp/

plans/INDEX.md

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+# Plans Index
+
+Living docs for upcoming or in-flight work, plus reference audits. Each
+entry lists status against the codebase as of the last review.
+
+| Plan | Topic | Status |
+|---|---|---|
+| [cloud-storage-readiness.md](./cloud-storage-readiness.md) | Decouple file I/O from parsers; add `Storage` interface + GCS adapter so `gs://` URIs work alongside local paths | Proposed |
+| [run_erc.md](./run_erc.md) | New `run_erc` MCP tool for net-level electrical rule checks (single_pin, testpoint_only, unnamed, testpoint_stub) | Proposed |
+| [xnet-depth-limit.md](./xnet-depth-limit.md) | Add `max_depth` parameter to `query_xnet_*` tools, plus `max_depth_reached` and `frontier_nets` response metadata | Proposed |
+| [power-net-stop-pattern.md](./power-net-stop-pattern.md) | Switch `POWER_NET_PATTERN` / `STOP_NET_PATTERN` keywords (VCC/VDD/VBAT/VBUS/VSYS) from anchored prefix to substring matching so prefixed rails like `CC1310_VDD` stop traversal | Proposed |
+| [relative_path.md](./relative_path.md) | Auto-discovery + ID-based design access: `list_designs` returns relative-path IDs that all other tools accept instead of absolute paths | Proposed |
+| [altium-visual-data.md](./altium-visual-data.md) | Extract non-electrical visual/drawing data (lines, polylines, junctions, sheet metadata, etc.) from `.SchDoc` for future schematic rendering | Proposed |
+| [dsn-parser-audit.md](./dsn-parser-audit.md) | Audit comparing our DSN TypeScript parser against the C++ `OpenOrCadParser` reference. Documents semantic extensions, gaps, and risks | Reference |
+
+## Conventions
+
+- One file per plan, named with kebab-case where practical.
+- Each plan should open with a `## Context` section explaining *why* the
+  change is needed before describing *what* to build.
+- Plans stay in this folder until landed. After implementation, either
+  delete the file (if the plan is fully captured by the code + commit
+  history) or move to `docs/` if the writeup has long-term reference value
+  (the DSN audit is an example of the latter).

plans/altium-visual-data.md

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+# Altium Schematic Visual Data Extraction
+
+**Goal**: Extract non-electrical visual/drawing data from `.SchDoc` files for future schematic rendering.
+
+**Context**: The current Altium parser (`src/parsers/altium/`) only extracts electrical data (components, pins, nets) into the unified `ParsedNetlist` model. However, `.SchDoc` files contain rich visual information that could enable schematic rendering in a browser (e.g., in `pcb-viewer` or a new `schematic-viewer`).
+
+**Reference**: The [Altium-Schematic-Parser](https://github.com/a3ng7n/Altium-Schematic-Parser) project demonstrates raw record-level extraction of all 51 record types, including drawing primitives. It can serve as a reference for what data is available.
+
+**Data to extract** (record types not currently used):
+
+| Record | Type | Visual Data |
+|--------|------|-------------|
+| 4 | Annotation | Text boxes with position, color, font |
+| 5 | Bezier | Bezier curve coordinates |
+| 6 | Polyline | Line segments with X/Y coordinates, color, width |
+| 7 | Polygon | Filled polygonal regions |
+| 8 | Ellipse | Elliptical shapes |
+| 10 | Round Rectangle | Rounded rectangles |
+| 11 | Elliptical Arc | Arc segments |
+| 12 | Arc | Circular arcs |
+| 13 | Line | Simple lines |
+| 14 | Rectangle | Rectangular shapes |
+| 28 | Text Frame | Text with bounding box |
+| 29 | Junction | Wire junction dots |
+| 30 | Image | Embedded images |
+| 31 | Sheet | Page size, grid, title block, border |
+| 32 | Sheet Name | Sheet title |
+| 33 | Sheet File Name | File reference |
+| 34 | Designator | Component designator text with position/font |
+| 39 | Template | Title block template reference |
+| 44/45 | Model Container/Reference | Symbol geometry from library |
+
+**Notes**:
+- This data is NOT for MCP tool responses; it is for rendering schematics visually.
+- Parsing should produce a separate visual model alongside `ParsedNetlist`, not pollute the electrical data.
+- Pin coordinates, wire coordinates, and component positions are already partially available but discarded after connectivity resolution.
+- The standalone parser uses geometry-based connectivity (bounding box intersection), while universal-netlist uses Union-Find with spatial grid indexing. The visual extraction should reuse the existing OLE/record parsing infrastructure.