AMD GPU support: HIP/ROCm via single-source backend_gpu_compat.h (+ WMMA dispatch gate)

[noobdev-ph]

Summary

The AMD half of #112, rebuilt against dev as requested — one thing only: the existing CUDA backend compiles unchanged for AMD GPUs via ROCm (make HIP=1), through a 62-line mapping header, the same one-shim pattern compat.h uses for the Windows port. 5 files, +218/−15; backend_cuda.cu itself changes by 7 lines; glm.c untouched.

• backend_gpu_compat.h: under nvcc, a pass-through to cuda_runtime.h+mma.h — the NVIDIA path's preprocessed source is byte-identical to today's, which your CI can verify. Under hipcc, the CUDA runtime surface maps to HIP 1:1.
• WMMA gating (COLI_GPU_HAS_WMMA) — this part matters beyond AMD: the tensor-core kernel bodies are __CUDA_ARCH__ >= 700-guarded, but the host dispatch checks compute_major >= 7 at runtime. gfx GPUs report compute_major = 12, so without the compile-time gate the dispatch selects empty kernel bodies and silently returns garbage on any non-CUDA target. HIP uses the portable kernels; rocWMMA is a natural follow-up.
• Makefile: HIP=1/HIP_ARCH, hip-test, gpu-compile (CI compile-only), a GPUCC indirection so all GPU rules stay single-path, and HIP flags joined to your new .build-config stamp so HIP↔CPU flag flips relink correctly (Benchmark + Windows GPU-build fixes: GLM-5.2 on Core Ultra 9 285K + RTX 5080 (sm_120) #306's fix extended, not bypassed).
• CI: an engine-hip-syntax job mirroring your engine-cuda-syntax (rocm/dev container — tag pinned and disk pre-freed; latest no longer fits hosted runners, details in the job comments).

On "verified rather than trusted" — the honest position

Hosted CI proves compilation; runtime verification necessarily comes from community AMD hardware — the same epistemology as the README's benchmark table. What this PR offers concretely: (1) the CUDA path is provably unchanged (byte-identical preprocessing — verifiable by anyone); (2) hip-test runs the full upstream test suite (incl. tensor_update) on my RX 9070 XT — pass, 5/5 repeat runs; (3) end-to-end: GLM-5.2 at 0.33 tok/s / 60% expert hit with CUDA_RELEASE_HOST=1 on this dev rebase (CPU: 0.22–0.27 same machine) — full setup documented in GPU_BACKENDS.md so any AMD owner can reproduce; (4) I commit to running hip-test + an end-to-end check against dev on request and on releases, and to first-responding AMD issues. If you'd rather see a second independent AMD datapoint before merging, keeping this open until one arrives is a reasonable call — the branch is maintained either way.

Validation

• make -C c check — CPU untouched
• hip-test on gfx1201 (ROCm 7.2.4): full suite pass
• nvcc path: byte-identical preprocessed source (pass-through include)
• engine-hip-syntax runs in your CI structure

Compatibility

• Default CPU build dependency-free; HIP=1 opt-in, Linux-only, mutually exclusive with CUDA=1, errors early
• No model files, binaries, or artifacts

Companion PR: #338 (vendor-neutral backend hardening — independently mergeable).