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CoreThreadScheduling
Hybrid preemptive/cooperative thread scheduler with yieldpoints and TSI.
JNode implements a hybrid preemptive/cooperative multithreading system that balances responsiveness with efficiency. The scheduler combines hardware timer interrupts (preemptive) with compiler-inserted yieldpoints (cooperative) to achieve optimal thread management for a Java operating system.
The preemptive component ensures no thread monopolizes the CPU for extended periods, while the cooperative component (yieldpoints) allows threads to voluntarily yield before their timeslice expires, improving responsiveness for I/O-bound tasks. This design minimizes context-switch overhead while maintaining system responsiveness.
| Class / File | Role |
|---|---|
core/src/core/org/jnode/vm/scheduler/TSI.java |
Thread state indicator constants |
core/src/core/org/jnode/vm/scheduler/ThreadScheduler.java |
Global scheduler with priority queues |
core/src/core/org/jnode/vm/scheduler/Dispatcher.java |
Thread dispatcher and context switching |
core/src/core/org/jnode/vm/scheduler/VmProcessor.java |
Per-CPU state and TSI management |
core/src/core/org/jnode/vm/scheduler/VmThread.java |
Thread state and execution context |
core/src/core/org/jnode/vm/scheduler/VmThreadQueue.java |
Priority/time-sorted thread queues |
core/src/native/x86/vm-ints.asm |
Assembly handlers for yieldpoints and timer |
The scheduler combines two mechanisms:
-
Preemptive Component: Hardware timer interrupts (PIT/APIC) periodically set the
TSI_SWITCH_NEEDEDflag, forcing thread switches. Frequency is configurable, typically every few milliseconds. -
Cooperative Component: Yieldpoints are compiler-inserted checks in compiled Java code. When a thread reaches a yieldpoint and the TSI indicates a switch is needed, it voluntarily yields the CPU.
The TSI is a per-processor flag word (Word type for atomic operations):
| Flag | Value | Purpose |
|---|---|---|
TSI_SWITCH_NEEDED |
0x0001 | Thread switch requested |
TSI_SYSTEM_READY |
0x0002 | System init complete, switches allowed |
TSI_SWITCH_ACTIVE |
0x0004 | Thread switch in progress |
TSI_BLOCK_SWITCH |
0x0008 | Block all switches (GC, monitors) |
Atomic operations use Word.atomicOr() and Word.atomicAnd() for safe state transitions.
- Compiled code tests TSI against
TSI_SWITCH_REQUESTED(0x0003) - If flags match, triggers software interrupt
YIELDPOINT_INTNO - Assembly handler saves current thread registers
- Calls
VmProcessor.reschedule() - Selects highest-priority ready thread
- Restores new thread registers and resumes
In VmProcessor.reschedule():
- Process kernel debugger input (if enabled)
- Dispatch pending interrupts via IRQ manager
- Re-queue current thread if still in RUNNING state
- Wake up sleeping threads whose wakeup time has passed
- Select highest-priority ready thread from queue
- If no thread available, run the idle thread
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Yieldpoint placement: Compiler inserts yieldpoints at method entries, loop headers, and back-edges. Conditional yieldpoints appear every ~1000 loop iterations to balance overhead vs responsiveness.
-
@Uninterruptible restriction: Methods annotated with
@Uninterruptibleskip yieldpoint insertion for performance, critical for VM internals. -
TSI atomicity requirement: State transitions MUST use atomic operations. Non-atomic updates can cause race conditions in multi-CPU systems.
-
TSI_BLOCK_SWITCH usage: Used during garbage collection and monitor operations to prevent unexpected context switches at critical points.
-
FPU/XMM lazy save/restore: Floating-point state is saved/restored lazily to reduce context-switch overhead for threads that don't use FPU.
-
Stack overflow detection: Limited slots (256) before stack boundary; overflow handling requires careful assembly-level checks.
-
Idle thread fallback: When no ready threads exist, the idle thread runs to prevent CPU starvation.
- TSI - Thread State Indicator bit flags and atomic operations
- Yieldpoint - Compiler-inserted yieldpoint mechanism
- Thread-Scheduling - Thread scheduling concepts
- Core-Thread-Scheduling - (self reference)
- Interrupt-Handling - Hardware interrupt handling
- Architecture - Overall system architecture