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sail: implement HL.CCAT/HL.CCATW #76

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sail: implement HL.CCAT/HL.CCATW #76

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6fcde44
sail: implement HL.BFI using wrap-around bitfield model
zhoubot Mar 2, 2026
9dfbb02
sail: implement HL.MIADD/MISUB (mul-add/sub with imm19)
zhoubot Mar 2, 2026
68327ef
sail: implement HL.CCAT/HL.CCATW (128-bit concat then shift-left)
zhoubot Mar 2, 2026
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2 changes: 1 addition & 1 deletion isa/sail/coverage.json
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{"implemented_forms":495,"implemented_list":"isa/sail/implemented_mnemonics.txt","implemented_mnemonics":["ADD","ADDI","ADDIW","ADDTPC","ADDW","AND","ANDI","ANDIW","ANDW","ASSERT","B.ARG","B.ATTR","B.DIM","B.EQ","B.GE","B.GEU","B.HINT","B.IOD","B.IOR","B.IOT","B.IOTI","B.LT","B.LTU","B.NE","B.NZ","B.TEXT","B.Z","BC.IALL","BC.IVA","BCNT","BIC","BIS","BSE","BSTART","BSTART CALL","BSTART.ACCCVT","BSTART.CUBE","BSTART.FIXP","BSTART.FP","BSTART.MPAR","BSTART.MSEQ","BSTART.PAR","BSTART.STD","BSTART.SYS","BSTART.TEPL","BSTART.TLOAD","BSTART.TMA","BSTART.TMATMUL","BSTART.TMATMUL.ACC","BSTART.TMOV","BSTART.TSTORE","BSTART.VPAR","BSTART.VSEQ","BSTOP","BWE","BWI","BWT","BXS","BXU","C.ADD","C.ADDI","C.AND","C.B.DIM","C.B.DIMI","C.BSTART","C.BSTART.FP","C.BSTART.MPAR","C.BSTART.MSEQ","C.BSTART.STD","C.BSTART.SYS","C.BSTART.VPAR","C.BSTART.VSEQ","C.BSTOP","C.CMP.EQI","C.CMP.NEI","C.EBREAK","C.LDI","C.LWI","C.MOVI","C.MOVR","C.OR","C.SDI","C.SETC.EQ","C.SETC.NE","C.SETC.TGT","C.SETRET","C.SEXT.B","C.SEXT.H","C.SEXT.W","C.SLLI","C.SRLI","C.SUB","C.SWI","C.ZEXT.B","C.ZEXT.H","C.ZEXT.W","CLZ","CMP.AND","CMP.ANDI","CMP.EQ","CMP.EQI","CMP.GE","CMP.GEI","CMP.GEU","CMP.GEUI","CMP.LT","CMP.LTI","CMP.LTU","CMP.LTUI","CMP.NE","CMP.NEI","CMP.OR","CMP.ORI","CSEL","CTZ","DC.CISW","DC.CIVA","DC.CSW","DC.CVA","DC.IALL","DC.ISW","DC.IVA","DC.ZVA","DIV","DIVU","DIVUW","DIVW","EBREAK","FABS","FENCE.D","FENCE.I","FEQ","FEQS","FGE","FGES","FLT","FLTS","FMAX","FMIN","FNE","FNES","HL.ADDTPC","HL.ANDI","HL.ANDIW","HL.BSTART.FP","HL.BSTART.STD","HL.CASB","HL.CASD","HL.CASH","HL.CASW","HL.CMP.ANDI","HL.CMP.EQI","HL.CMP.GEI","HL.CMP.GEUI","HL.CMP.LTI","HL.CMP.LTUI","HL.CMP.NEI","HL.CMP.ORI","HL.DIV","HL.DIVU","HL.DIVUW","HL.DIVW","HL.LB.PCR","HL.LB.PO","HL.LB.PR","HL.LBI","HL.LBI.PO","HL.LBI.PR","HL.LBIP","HL.LBP","HL.LBU.PCR","HL.LBU.PO","HL.LBU.PR","HL.LBUI","HL.LBUI.PO","HL.LBUI.PR","HL.LBUIP","HL.LBUP","HL.LD.PCR","HL.LD.PO","HL.LD.PR","HL.LDI","HL.LDI.PO","HL.LDI.PR","HL.LDI.U","HL.LDI.UPO","HL.LDI.UPR","HL.LDIP","HL.LDIP.U","HL.LDP","HL.LH.PCR","HL.LH.PO","HL.LH.PR","HL.LHI","HL.LHI.PO","HL.LHI.PR","HL.LHI.U","HL.LHI.UPO","HL.LHI.UPR","HL.LHIP","HL.LHIP.U","HL.LHP","HL.LHU.PCR","HL.LHU.PO","HL.LHU.PR","HL.LHUI","HL.LHUI.PO","HL.LHUI.PR","HL.LHUI.U","HL.LHUI.UPO","HL.LHUI.UPR","HL.LHUIP","HL.LHUIP.U","HL.LHUP","HL.LIS","HL.LIU","HL.LUI","HL.LW.PCR","HL.LW.PO","HL.LW.PR","HL.LWI","HL.LWI.PO","HL.LWI.PR","HL.LWI.U","HL.LWI.UPO","HL.LWI.UPR","HL.LWIP","HL.LWIP.U","HL.LWP","HL.LWU.PCR","HL.LWU.PO","HL.LWU.PR","HL.LWUI","HL.LWUI.PO","HL.LWUI.PR","HL.LWUI.U","HL.LWUI.UPO","HL.LWUI.UPR","HL.LWUIP","HL.LWUIP.U","HL.LWUP","HL.MADD","HL.MADDW","HL.MUL","HL.MULU","HL.ORI","HL.ORIW","HL.PRF","HL.PRF.A","HL.PRFI.U","HL.PRFI.UA","HL.REM","HL.REMU","HL.REMUW","HL.REMW","HL.SB.PCR","HL.SB.PO","HL.SB.PR","HL.SBI","HL.SBI.PO","HL.SBI.PR","HL.SBIP","HL.SBP","HL.SD.PCR","HL.SD.PO","HL.SD.PR","HL.SDI","HL.SDI.PO","HL.SDI.PR","HL.SDI.U","HL.SDI.UPO","HL.SDI.UPR","HL.SDIP","HL.SDIP.U","HL.SDP","HL.SDP.U","HL.SETC.ANDI","HL.SETC.EQI","HL.SETC.GEI","HL.SETC.GEUI","HL.SETC.LTI","HL.SETC.LTUI","HL.SETC.NEI","HL.SETC.ORI","HL.SETRET","HL.SH.PCR","HL.SH.PO","HL.SH.PR","HL.SHI","HL.SHI.PO","HL.SHI.PR","HL.SHI.U","HL.SHI.UPO","HL.SHI.UPR","HL.SHIP","HL.SHIP.U","HL.SHP","HL.SHP.U","HL.SW.PCR","HL.SW.PO","HL.SW.PR","HL.SWI","HL.SWI.PO","HL.SWI.PR","HL.SWI.U","HL.SWI.UPO","HL.SWI.UPR","HL.SWIP","HL.SWIP.U","HL.SWP","HL.SWP.U","HL.XORI","HL.XORIW","IC.IALL","IC.IVA","J","JR","LB","LB.PCR","LBI","LBU","LBU.PCR","LBUI","LD","LD.ADD","LD.AND","LD.OR","LD.PCR","LD.SMAX","LD.SMIN","LD.UMAX","LD.UMIN","LD.XOR","LDI","LDI.U","LH","LH.PCR","LHI","LHU","LHU.PCR","LHUI","LR.B","LR.D","LR.H","LR.W","LUI","LW","LW.ADD","LW.AND","LW.OR","LW.PCR","LW.SMAX","LW.SMIN","LW.UMAX","LW.UMIN","LW.XOR","LWI","LWU","LWU.PCR","LWUI","MADD","MADDW","MAX","MAXU","MIN","MINU","MUL","MULU","MULUW","MULW","OR","ORI","ORIW","ORW","PRF","PRFI.U","REM","REMU","REMUW","REMW","REV","ROR","SB","SB.PCR","SBI","SC.B","SC.D","SC.H","SC.W","SD","SD.ADD","SD.AND","SD.OR","SD.PCR","SD.SMAX","SD.SMIN","SD.U","SD.UMAX","SD.UMIN","SD.XOR","SDI","SDI.U","SETC.AND","SETC.ANDI","SETC.EQ","SETC.EQI","SETC.GE","SETC.GEI","SETC.GEU","SETC.GEUI","SETC.LT","SETC.LTI","SETC.LTU","SETC.LTUI","SETC.NE","SETC.NEI","SETC.OR","SETC.ORI","SETC.TGT","SETRET","SH","SH.PCR","SH.U","SHI","SHI.U","SLL","SLLI","SLLIW","SLLW","SRA","SRAI","SRAIW","SRAW","SRL","SRLI","SRLIW","SRLW","SUB","SUBI","SUBIW","SUBW","SW","SW.ADD","SW.AND","SW.OR","SW.PCR","SW.SMAX","SW.SMIN","SW.U","SW.UMAX","SW.UMIN","SW.XOR","SWAPB","SWAPD","SWAPH","SWAPW","SWI","SWI.U","TLB.IA","TLB.IALL","TLB.IAV","TLB.IV","XOR","XORI","XORIW","XORW"],"missing_forms":245,"missing_mnemonics":["ACRC","ACRE","C.SSRGET","ERCOV","ESAVE","FADD","FCVT","FCVTA","FCVTM","FCVTN","FCVTP","FCVTZ","FDIV","FENTRY","FEXIT","FEXP","FMADD","FMSUB","FMUL","FNMADD","FNMSUB","FRECIP","FRET.RA","FRET.STK","FSQRT","FSUB","HL.ADDI","HL.ADDIW","HL.BFI","HL.BSTART CALL","HL.BSTART.SYS","HL.CCAT","HL.CCATW","HL.MIADD","HL.MISUB","HL.QMT","HL.QPOP","HL.QPUSH","HL.SD.UPO","HL.SD.UPR","HL.SH.UPO","HL.SH.UPR","HL.SSRGET","HL.SSRSET","HL.SUBI","HL.SUBIW","HL.SW.UPO","HL.SW.UPR","LHI.U","LHUI.U","LSRGET","LWI.U","LWUI.U","MCOPY","MSET","SCVTF","SSRGET","SSRSET","SSRSWAP","UCVTF","V.ADD","V.ADDI","V.AND","V.ANDI","V.BCNT","V.BIC","V.BIS","V.BXS","V.BXU","V.CLZ","V.CMP.AND","V.CMP.ANDI","V.CMP.EQ","V.CMP.EQI","V.CMP.GE","V.CMP.GEI","V.CMP.GEU","V.CMP.GEUI","V.CMP.LT","V.CMP.LTI","V.CMP.LTU","V.CMP.LTUI","V.CMP.NE","V.CMP.NEI","V.CMP.OR","V.CMP.ORI","V.CSEL","V.CTZ","V.DIV","V.FABS","V.FADD","V.FCLASS","V.FCVT","V.FCVTI","V.FDIV","V.FEQ","V.FEQS","V.FEXP","V.FGE","V.FGES","V.FLT","V.FLTS","V.FMADD","V.FMAX","V.FMIN","V.FMSUB","V.FMUL","V.FNE","V.FNES","V.FNMADD","V.FNMSUB","V.FRECIP","V.FSQRT","V.FSUB","V.ICVT","V.ICVTF","V.LB","V.LB.BRG","V.LBI","V.LBI.BRG","V.LBU","V.LBU.BRG","V.LBUI","V.LBUI.BRG","V.LD","V.LD.ADD","V.LD.AND","V.LD.BRG","V.LD.MAX","V.LD.MIN","V.LD.OR","V.LD.XOR","V.LDI","V.LDI.BRG","V.LDI.U","V.LDI.U.BRG","V.LH","V.LH.BRG","V.LHI","V.LHI.BRG","V.LHI.U","V.LHI.U.BRG","V.LHU","V.LHU.BRG","V.LHUI","V.LHUI.BRG","V.LHUI.U","V.LHUI.U.BRG","V.LW","V.LW.ADD","V.LW.AND","V.LW.BRG","V.LW.MAX","V.LW.MIN","V.LW.OR","V.LW.XOR","V.LWI","V.LWI.BRG","V.LWI.U","V.LWI.U.BRG","V.LWU","V.LWU.BRG","V.LWUI","V.LWUI.BRG","V.LWUI.U","V.LWUI.U.BRG","V.MADD","V.MAX","V.MIN","V.MUL","V.OR","V.ORI","V.PSEL","V.QPOP","V.QPUSH","V.RDADD","V.RDAND","V.RDFADD","V.RDFMAX","V.RDFMIN","V.RDMAX","V.RDMIN","V.RDOR","V.RDXOR","V.REM","V.REV","V.SB","V.SB.BRG","V.SBI","V.SBI.BRG","V.SD","V.SD.ADD","V.SD.AND","V.SD.BRG","V.SD.MAX","V.SD.MIN","V.SD.OR","V.SD.U","V.SD.U.BRG","V.SD.XOR","V.SDI","V.SDI.BRG","V.SDI.U","V.SDI.U.BRG","V.SH","V.SH.BRG","V.SH.U","V.SH.U.BRG","V.SHFL.BFLY","V.SHFL.DOWN","V.SHFL.IDX","V.SHFL.UP","V.SHFLI.BFLY","V.SHFLI.DOWN","V.SHFLI.IDX","V.SHFLI.UP","V.SHI","V.SHI.BRG","V.SHI.U","V.SHI.U.BRG","V.SLL","V.SLLI","V.SRA","V.SRAI","V.SRL","V.SRLI","V.SUB","V.SUBI","V.SW","V.SW.ADD","V.SW.AND","V.SW.BRG","V.SW.MAX","V.SW.MIN","V.SW.OR","V.SW.U","V.SW.U.BRG","V.SW.XOR","V.SWI","V.SWI.BRG","V.SWI.U","V.SWI.U.BRG","V.XOR","V.XORI","XB"],"spec":"isa/v0.3/linxisa-v0.3.json","total_forms":740}
{"implemented_forms":500,"implemented_list":"isa/sail/implemented_mnemonics.txt","implemented_mnemonics":["ADD","ADDI","ADDIW","ADDTPC","ADDW","AND","ANDI","ANDIW","ANDW","ASSERT","B.ARG","B.ATTR","B.DIM","B.EQ","B.GE","B.GEU","B.HINT","B.IOD","B.IOR","B.IOT","B.IOTI","B.LT","B.LTU","B.NE","B.NZ","B.TEXT","B.Z","BC.IALL","BC.IVA","BCNT","BIC","BIS","BSE","BSTART","BSTART CALL","BSTART.ACCCVT","BSTART.CUBE","BSTART.FIXP","BSTART.FP","BSTART.MPAR","BSTART.MSEQ","BSTART.PAR","BSTART.STD","BSTART.SYS","BSTART.TEPL","BSTART.TLOAD","BSTART.TMA","BSTART.TMATMUL","BSTART.TMATMUL.ACC","BSTART.TMOV","BSTART.TSTORE","BSTART.VPAR","BSTART.VSEQ","BSTOP","BWE","BWI","BWT","BXS","BXU","C.ADD","C.ADDI","C.AND","C.B.DIM","C.B.DIMI","C.BSTART","C.BSTART.FP","C.BSTART.MPAR","C.BSTART.MSEQ","C.BSTART.STD","C.BSTART.SYS","C.BSTART.VPAR","C.BSTART.VSEQ","C.BSTOP","C.CMP.EQI","C.CMP.NEI","C.EBREAK","C.LDI","C.LWI","C.MOVI","C.MOVR","C.OR","C.SDI","C.SETC.EQ","C.SETC.NE","C.SETC.TGT","C.SETRET","C.SEXT.B","C.SEXT.H","C.SEXT.W","C.SLLI","C.SRLI","C.SUB","C.SWI","C.ZEXT.B","C.ZEXT.H","C.ZEXT.W","CLZ","CMP.AND","CMP.ANDI","CMP.EQ","CMP.EQI","CMP.GE","CMP.GEI","CMP.GEU","CMP.GEUI","CMP.LT","CMP.LTI","CMP.LTU","CMP.LTUI","CMP.NE","CMP.NEI","CMP.OR","CMP.ORI","CSEL","CTZ","DC.CISW","DC.CIVA","DC.CSW","DC.CVA","DC.IALL","DC.ISW","DC.IVA","DC.ZVA","DIV","DIVU","DIVUW","DIVW","EBREAK","FABS","FENCE.D","FENCE.I","FEQ","FEQS","FGE","FGES","FLT","FLTS","FMAX","FMIN","FNE","FNES","HL.ADDTPC","HL.ANDI","HL.ANDIW","HL.BFI","HL.BSTART.FP","HL.BSTART.STD","HL.CASB","HL.CASD","HL.CASH","HL.CASW","HL.CCAT","HL.CCATW","HL.CMP.ANDI","HL.CMP.EQI","HL.CMP.GEI","HL.CMP.GEUI","HL.CMP.LTI","HL.CMP.LTUI","HL.CMP.NEI","HL.CMP.ORI","HL.DIV","HL.DIVU","HL.DIVUW","HL.DIVW","HL.LB.PCR","HL.LB.PO","HL.LB.PR","HL.LBI","HL.LBI.PO","HL.LBI.PR","HL.LBIP","HL.LBP","HL.LBU.PCR","HL.LBU.PO","HL.LBU.PR","HL.LBUI","HL.LBUI.PO","HL.LBUI.PR","HL.LBUIP","HL.LBUP","HL.LD.PCR","HL.LD.PO","HL.LD.PR","HL.LDI","HL.LDI.PO","HL.LDI.PR","HL.LDI.U","HL.LDI.UPO","HL.LDI.UPR","HL.LDIP","HL.LDIP.U","HL.LDP","HL.LH.PCR","HL.LH.PO","HL.LH.PR","HL.LHI","HL.LHI.PO","HL.LHI.PR","HL.LHI.U","HL.LHI.UPO","HL.LHI.UPR","HL.LHIP","HL.LHIP.U","HL.LHP","HL.LHU.PCR","HL.LHU.PO","HL.LHU.PR","HL.LHUI","HL.LHUI.PO","HL.LHUI.PR","HL.LHUI.U","HL.LHUI.UPO","HL.LHUI.UPR","HL.LHUIP","HL.LHUIP.U","HL.LHUP","HL.LIS","HL.LIU","HL.LUI","HL.LW.PCR","HL.LW.PO","HL.LW.PR","HL.LWI","HL.LWI.PO","HL.LWI.PR","HL.LWI.U","HL.LWI.UPO","HL.LWI.UPR","HL.LWIP","HL.LWIP.U","HL.LWP","HL.LWU.PCR","HL.LWU.PO","HL.LWU.PR","HL.LWUI","HL.LWUI.PO","HL.LWUI.PR","HL.LWUI.U","HL.LWUI.UPO","HL.LWUI.UPR","HL.LWUIP","HL.LWUIP.U","HL.LWUP","HL.MADD","HL.MADDW","HL.MIADD","HL.MISUB","HL.MUL","HL.MULU","HL.ORI","HL.ORIW","HL.PRF","HL.PRF.A","HL.PRFI.U","HL.PRFI.UA","HL.REM","HL.REMU","HL.REMUW","HL.REMW","HL.SB.PCR","HL.SB.PO","HL.SB.PR","HL.SBI","HL.SBI.PO","HL.SBI.PR","HL.SBIP","HL.SBP","HL.SD.PCR","HL.SD.PO","HL.SD.PR","HL.SDI","HL.SDI.PO","HL.SDI.PR","HL.SDI.U","HL.SDI.UPO","HL.SDI.UPR","HL.SDIP","HL.SDIP.U","HL.SDP","HL.SDP.U","HL.SETC.ANDI","HL.SETC.EQI","HL.SETC.GEI","HL.SETC.GEUI","HL.SETC.LTI","HL.SETC.LTUI","HL.SETC.NEI","HL.SETC.ORI","HL.SETRET","HL.SH.PCR","HL.SH.PO","HL.SH.PR","HL.SHI","HL.SHI.PO","HL.SHI.PR","HL.SHI.U","HL.SHI.UPO","HL.SHI.UPR","HL.SHIP","HL.SHIP.U","HL.SHP","HL.SHP.U","HL.SW.PCR","HL.SW.PO","HL.SW.PR","HL.SWI","HL.SWI.PO","HL.SWI.PR","HL.SWI.U","HL.SWI.UPO","HL.SWI.UPR","HL.SWIP","HL.SWIP.U","HL.SWP","HL.SWP.U","HL.XORI","HL.XORIW","IC.IALL","IC.IVA","J","JR","LB","LB.PCR","LBI","LBU","LBU.PCR","LBUI","LD","LD.ADD","LD.AND","LD.OR","LD.PCR","LD.SMAX","LD.SMIN","LD.UMAX","LD.UMIN","LD.XOR","LDI","LDI.U","LH","LH.PCR","LHI","LHU","LHU.PCR","LHUI","LR.B","LR.D","LR.H","LR.W","LUI","LW","LW.ADD","LW.AND","LW.OR","LW.PCR","LW.SMAX","LW.SMIN","LW.UMAX","LW.UMIN","LW.XOR","LWI","LWU","LWU.PCR","LWUI","MADD","MADDW","MAX","MAXU","MIN","MINU","MUL","MULU","MULUW","MULW","OR","ORI","ORIW","ORW","PRF","PRFI.U","REM","REMU","REMUW","REMW","REV","ROR","SB","SB.PCR","SBI","SC.B","SC.D","SC.H","SC.W","SD","SD.ADD","SD.AND","SD.OR","SD.PCR","SD.SMAX","SD.SMIN","SD.U","SD.UMAX","SD.UMIN","SD.XOR","SDI","SDI.U","SETC.AND","SETC.ANDI","SETC.EQ","SETC.EQI","SETC.GE","SETC.GEI","SETC.GEU","SETC.GEUI","SETC.LT","SETC.LTI","SETC.LTU","SETC.LTUI","SETC.NE","SETC.NEI","SETC.OR","SETC.ORI","SETC.TGT","SETRET","SH","SH.PCR","SH.U","SHI","SHI.U","SLL","SLLI","SLLIW","SLLW","SRA","SRAI","SRAIW","SRAW","SRL","SRLI","SRLIW","SRLW","SUB","SUBI","SUBIW","SUBW","SW","SW.ADD","SW.AND","SW.OR","SW.PCR","SW.SMAX","SW.SMIN","SW.U","SW.UMAX","SW.UMIN","SW.XOR","SWAPB","SWAPD","SWAPH","SWAPW","SWI","SWI.U","TLB.IA","TLB.IALL","TLB.IAV","TLB.IV","XOR","XORI","XORIW","XORW"],"missing_forms":240,"missing_mnemonics":["ACRC","ACRE","C.SSRGET","ERCOV","ESAVE","FADD","FCVT","FCVTA","FCVTM","FCVTN","FCVTP","FCVTZ","FDIV","FENTRY","FEXIT","FEXP","FMADD","FMSUB","FMUL","FNMADD","FNMSUB","FRECIP","FRET.RA","FRET.STK","FSQRT","FSUB","HL.ADDI","HL.ADDIW","HL.BSTART CALL","HL.BSTART.SYS","HL.QMT","HL.QPOP","HL.QPUSH","HL.SD.UPO","HL.SD.UPR","HL.SH.UPO","HL.SH.UPR","HL.SSRGET","HL.SSRSET","HL.SUBI","HL.SUBIW","HL.SW.UPO","HL.SW.UPR","LHI.U","LHUI.U","LSRGET","LWI.U","LWUI.U","MCOPY","MSET","SCVTF","SSRGET","SSRSET","SSRSWAP","UCVTF","V.ADD","V.ADDI","V.AND","V.ANDI","V.BCNT","V.BIC","V.BIS","V.BXS","V.BXU","V.CLZ","V.CMP.AND","V.CMP.ANDI","V.CMP.EQ","V.CMP.EQI","V.CMP.GE","V.CMP.GEI","V.CMP.GEU","V.CMP.GEUI","V.CMP.LT","V.CMP.LTI","V.CMP.LTU","V.CMP.LTUI","V.CMP.NE","V.CMP.NEI","V.CMP.OR","V.CMP.ORI","V.CSEL","V.CTZ","V.DIV","V.FABS","V.FADD","V.FCLASS","V.FCVT","V.FCVTI","V.FDIV","V.FEQ","V.FEQS","V.FEXP","V.FGE","V.FGES","V.FLT","V.FLTS","V.FMADD","V.FMAX","V.FMIN","V.FMSUB","V.FMUL","V.FNE","V.FNES","V.FNMADD","V.FNMSUB","V.FRECIP","V.FSQRT","V.FSUB","V.ICVT","V.ICVTF","V.LB","V.LB.BRG","V.LBI","V.LBI.BRG","V.LBU","V.LBU.BRG","V.LBUI","V.LBUI.BRG","V.LD","V.LD.ADD","V.LD.AND","V.LD.BRG","V.LD.MAX","V.LD.MIN","V.LD.OR","V.LD.XOR","V.LDI","V.LDI.BRG","V.LDI.U","V.LDI.U.BRG","V.LH","V.LH.BRG","V.LHI","V.LHI.BRG","V.LHI.U","V.LHI.U.BRG","V.LHU","V.LHU.BRG","V.LHUI","V.LHUI.BRG","V.LHUI.U","V.LHUI.U.BRG","V.LW","V.LW.ADD","V.LW.AND","V.LW.BRG","V.LW.MAX","V.LW.MIN","V.LW.OR","V.LW.XOR","V.LWI","V.LWI.BRG","V.LWI.U","V.LWI.U.BRG","V.LWU","V.LWU.BRG","V.LWUI","V.LWUI.BRG","V.LWUI.U","V.LWUI.U.BRG","V.MADD","V.MAX","V.MIN","V.MUL","V.OR","V.ORI","V.PSEL","V.QPOP","V.QPUSH","V.RDADD","V.RDAND","V.RDFADD","V.RDFMAX","V.RDFMIN","V.RDMAX","V.RDMIN","V.RDOR","V.RDXOR","V.REM","V.REV","V.SB","V.SB.BRG","V.SBI","V.SBI.BRG","V.SD","V.SD.ADD","V.SD.AND","V.SD.BRG","V.SD.MAX","V.SD.MIN","V.SD.OR","V.SD.U","V.SD.U.BRG","V.SD.XOR","V.SDI","V.SDI.BRG","V.SDI.U","V.SDI.U.BRG","V.SH","V.SH.BRG","V.SH.U","V.SH.U.BRG","V.SHFL.BFLY","V.SHFL.DOWN","V.SHFL.IDX","V.SHFL.UP","V.SHFLI.BFLY","V.SHFLI.DOWN","V.SHFLI.IDX","V.SHFLI.UP","V.SHI","V.SHI.BRG","V.SHI.U","V.SHI.U.BRG","V.SLL","V.SLLI","V.SRA","V.SRAI","V.SRL","V.SRLI","V.SUB","V.SUBI","V.SW","V.SW.ADD","V.SW.AND","V.SW.BRG","V.SW.MAX","V.SW.MIN","V.SW.OR","V.SW.U","V.SW.U.BRG","V.SW.XOR","V.SWI","V.SWI.BRG","V.SWI.U","V.SWI.U.BRG","V.XOR","V.XORI","XB"],"spec":"isa/v0.3/linxisa-v0.3.json","total_forms":740}
5 changes: 5 additions & 0 deletions isa/sail/implemented_mnemonics.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -104,6 +104,11 @@ SETC.ANDI
SETC.ORI

# HL (48-bit) immediate forms
HL.BFI
HL.MIADD
HL.MISUB
HL.CCAT
HL.CCATW
HL.CMP.EQI
HL.CMP.NEI
HL.CMP.LTI
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54 changes: 54 additions & 0 deletions isa/sail/model/execute/execute.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -430,6 +430,20 @@ function exec_bxs(RegDst : bits(5), SrcL : bits(5), Nminus1 : bits(6), M : bits(
write_regdst(RegDst, sext_low_n(f, n))
}

// HL.BFI: bitfield insert using the same wrap-around bitfield model as BXU/BXS.
// Insert a field extracted from SrcR (wrap field at {m,n}) into SrcL at the same wrap position.
function exec_hl_bfi(RegDst : bits(5), SrcL : bits(5), SrcR : bits(5), immr : bits(6), imms : bits(6)) -> unit = {
let x = read_reg5(SrcL);
let y = read_reg5(SrcR);
let n : int = unsigned(imms) + 1;
let m : int = unsigned(immr);
let field = bitfield_wrap(y, m, n);
// Clear the destination field in x at {m,n} and insert.
let xr = ror64(x, m);
let ins = (xr & (~mask_low_n(n))) | field;
write_regdst(RegDst, rol64(ins, m))
}

function exec_ror(RegDst : bits(5), SrcL : bits(5), M : bits(6)) -> unit = {
let x = read_reg5(SrcL);
let m : int = unsigned(M);
Expand Down Expand Up @@ -1239,6 +1253,46 @@ function exec_hl_mulu(RegDst0 : bits(5), RegDst1 : bits(5), SrcL : bits(5), SrcR
write_regdst(RegDst1, hi)
}

// HL.MIADD / HL.MISUB (user-confirmed): dst = SrcL ± (SrcR * uimm19), 64-bit wraparound.
function exec_hl_miadd(RegDst : bits(5), SrcL : bits(5), SrcR : bits(5), uimm19 : bits(19)) -> unit = {
let a = read_reg5(SrcL);
let b = read_reg5(SrcR);
let imm = zext19_to64(uimm19);
write_regdst(RegDst, a + (b * imm))
}

function exec_hl_misub(RegDst : bits(5), SrcL : bits(5), SrcR : bits(5), uimm19 : bits(19)) -> unit = {
let a = read_reg5(SrcL);
let b = read_reg5(SrcR);
let imm = zext19_to64(uimm19);
write_regdst(RegDst, a - (b * imm))
}

// -----------------------------------------------------------------------------
// HL (48-bit) concat/barrel ops: 128-bit concat then shift-left (user-confirmed)
//
// Semantics (confirmed):
// X128 = (SrcL << 64) | SrcR
// Y128 = X128 << shamt
// Dst0 = low64(Y128)
// Dst1 = high64(Y128)

function exec_hl_ccat(RegDst0 : bits(5), RegDst1 : bits(5), SrcL : bits(5), SrcR : bits(5), shamt : bits(7)) -> unit = {
let hi : bits(64) = read_reg5(SrcL);
let lo : bits(64) = read_reg5(SrcR);
let x128 : bits(128) = (zext64_to128(hi) << 64) | zext64_to128(lo);
let s : int = unsigned(shamt);
let y128 : bits(128) = if s == 0 then x128 else (x128 << s);
write_regdst(RegDst0, y128[63..0]);
write_regdst(RegDst1, y128[127..64])
}

function exec_hl_ccatw(RegDst0 : bits(5), RegDst1 : bits(5), SrcL : bits(5), SrcR : bits(5), shamt : bits(7)) -> unit = {
// For now CCATW shares the same 128-bit barrel-concat semantics as CCAT.
// If a future spec defines lane/word-specific behavior, refine here.
exec_hl_ccat(RegDst0, RegDst1, SrcL, SrcR, shamt)
}


// -----------------------------------------------------------------------------
// Multi-cycle ALU: multiply-add (three-source)
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