HengLiao updates to PyCircuit language#37

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hengliao1972 wants to merge 26 commits intoLinxISA:mainfrom

hengliao1972:main

Commits on Feb 10, 2026

Commits on Feb 11, 2026

Merge pull request #5 from Auyuir/traffic-lights-ce-pyc
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feat: add BF16 FMAC with 4-stage pipeline from primitive standard cells

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perf: reduce FMAC Stage 2 critical path from 46 to 28

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perf: split multiplier across pipeline stages for better balance

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Commits on Feb 12, 2026

feat: add FM16 system — 16 NPU full-mesh simulation with statistics

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feat: FM16 vs SW16 side-by-side topology comparison

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fix: show per-NPU bandwidth + SW16 bottleneck analysis

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fix: model SW5809s as 512×512 link / 128×128 port crossbar

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feat: model per-input-port independent ECMP RR and VOQ collision

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fix: SW5809s arbiter serves 1 pkt/egress-port/cycle (not 4)

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feat: add VOQ depth statistics to ECMP collision analysis

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Commits on Feb 25, 2026

Merge PR #6: Enhanced pyCircuit simulation/verification capability

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examples/fm16: sync fm16 updates (sw5809s.py)

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Commits on Mar 26, 2026

Merge branch 'LinxISA:main' into main
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fix(examples): put __future__ imports first in emulate scripts

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