feat: PyCircuit V5 — cycle-aware grammar, design migration, simulation speedup & cycle-balance optimization#45

Merged

hengliao1972 merged 27 commits intoLinxISA:mainfrom

hengliao1972:main

Mar 27, 2026

Commits on Feb 10, 2026

Commits on Feb 11, 2026

Merge pull request #5 from Auyuir/traffic-lights-ce-pyc
hengliao1972
authored
feat: add BF16 FMAC with 4-stage pipeline from primitive standard cells

authored and
Mac
committed
perf: reduce FMAC Stage 2 critical path from 46 to 28

authored and
Mac
committed
perf: split multiplier across pipeline stages for better balance

authored and
Mac
committed

Commits on Feb 12, 2026

feat: add FM16 system — 16 NPU full-mesh simulation with statistics

authored and
Mac
committed
feat: FM16 vs SW16 side-by-side topology comparison

authored and
Mac
committed
fix: show per-NPU bandwidth + SW16 bottleneck analysis

authored and
Mac
committed
fix: model SW5809s as 512×512 link / 128×128 port crossbar

authored and
Mac
committed
feat: model per-input-port independent ECMP RR and VOQ collision

authored and
Mac
committed
fix: SW5809s arbiter serves 1 pkt/egress-port/cycle (not 4)

authored and
Mac
committed
feat: add VOQ depth statistics to ECMP collision analysis

authored and
Mac
committed

Commits on Feb 25, 2026

Merge PR #6: Enhanced pyCircuit simulation/verification capability

Mac
authored and
Mac
committed
examples/fm16: sync fm16 updates (sw5809s.py)

authored and
Mac
committed

Commits on Mar 26, 2026

Merge branch 'LinxISA:main' into main
hengliao1972
authored
fix(examples): put __future__ imports first in emulate scripts

Mac
authored and
Mac
committed

Commits on Mar 27, 2026

feat: migrate all designs and testbenches to PyCircuit V5 cycle-aware syntax

Mac
authored and
Mac
committed