This project focuses on designing and implementing a multi-cycle RISC processor, integrating control logic, instruction memory, data memory, and functional units such as the ALU, register file, multiplexers, and PC control unit. The multi-cycle execution model ensures efficient instruction handling by breaking down execution into multiple stages: Instruction Fetch, Decode, Execute, Memory Access, and Write-Back.
- ✅ Design and implement a multi-cycle RISC processor.
- ✅ Develop an RTL architecture using Verilog.
- ✅ Simulate and test various instruction types (R-Type, I-Type, J-Type, Load/Store operations).
- ✅ Verify the processor’s functionality through waveform analysis.
- ✅ Optimize performance by structuring execution across multiple cycles.
- Stores the instructions to be executed by the processor.
- Fetches instructions in multiple cycles to allow sequential execution.
- Contains small, high-speed storage locations (registers) accessible by the processor.
- Supports register-based operations to enhance execution speed.
- Performs arithmetic and logical operations (e.g., ADD, SUB, AND, OR).
- Used during the execution phase of the pipeline.
- Stores and retrieves data required by load and store instructions.
- Handles memory access stages within the processor cycle.
- Direct control signals within the processor to select appropriate data paths.
- Sign extenders extend smaller bit-width values for proper execution.
- Manages instruction sequencing and branching logic.
- Updates the program counter based on instruction execution results.
- Generates control signals to regulate data flow and execution sequencing.
- Ensures proper coordination between different processor components.
The processor supports multiple instruction types categorized as:
- ADD, SUB, AND, OR
- Uses register-based operands and ALU computations.
- ADDI, ANDI, LW, SW, LBs, LBu
- Supports immediate values and memory interactions.
- JMP, CALL, RET
- Alters the program counter for function calls and returns.
- BEQ, BEQZ, BNE, BNEZ, BGT, BGTZ, BLT, BLTZ
- Implements conditional execution based on comparisons.
- Defines the multi-cycle execution states for each instruction.
- Created using Lucidchart for visual representation.
- Defines logic conditions to generate control signals.
- Controls ALU operations, memory access, and register updates.
- Designed and simulated using EDA Playground and Active-HDL.
- Comprises fetch, decode, execute, memory, and write-back stages.
- Written in Verilog with modular components for clarity and efficiency.
- Includes a testbench to verify functionality.
- ✅ Waveform Analysis: Validates execution correctness through test cases.
- ✅ Instruction Execution Validation: Ensures each instruction type functions correctly.
- ✅ Performance Optimization: Reduces cycle latency for improved efficiency.
Ensure you have the following installed:
- Verilog Compiler (EDA Playground, Active-HDL, ModelSim)
- Lucidchart (for diagrams)
- Git for version control
git clone https://github.com/mohammadkhdour/Multi-Cycle-RISC-Processor.git
cd Multi-Cycle-RISC-Processor- Open EDA Playground or Active-HDL.
- Load the Verilog files.
- Compile and simulate the processor.
- Observe the waveform output for validation.
Contributions are welcome! Fork this repository and submit a Pull Request.
This project is licensed under the MIT License.