Add hybrid ADRC+MPCC sim + Gen6 hardware demo (compare FOC/ADRC) - #40
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saeed95-lab wants to merge 41 commits into
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Add hybrid ADRC+MPCC sim + Gen6 hardware demo (compare FOC/ADRC)#40saeed95-lab wants to merge 41 commits into
saeed95-lab wants to merge 41 commits into
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Introduce Lib/Simulation (dq plant, eight-state VSI, MPCC/FOC runners and tests), the control.mpcc graph template, and docs/scripts so predictive current control can be verified on host before STM32 PWM adapter work.
- Add Assets/Examples/mpcc_demo.json: full FCS-MPCC hardware graph with phase currents, encoder, DC-link, FRAM config params, and telemetry. - Add Transforms.SwitchToDuty node: maps switch states (0/1) to 0%/100% duty for the existing Actuators.PwmOut. - Add Values.Config/constructor.cpp: restore platform_config_load() call that was dropped when config.value was renamed to Values.Config. - Fix control.mpcc: correct angular-velocity unit to au::radians/au::seconds, add port/parameter descriptions. - Fix CodeGenerator: treat Values.Config as a config node.
Conventional FCS picks S111 on low-L motors because one full vector predicts ~1000 A per step; Mode 3 applies deadbeat voltage through SVPWM so duties are continuous and Iq can track.
Bypass IqGate and stop CfgEnable from forcing ThrottleEnable off. Mode 3 now uses a shorter Ts_Eff plus residual current integrators so low-L deadbeat voltages are not lost to inverter deadtime.
…m/saeed95-lab/RTE into feature/fcs-mpcc-three-phase-pmsm
Reload Values.Config from FRAM in TimIsrStart, guard Poles<=0 in ElecAngle, and trip Mode 3 voltage when measured current exceeds I_Max.
Replace aggressive Ts_Eff/Ki and hard overcurrent trip with FOC-like gains, voltage LPF, soft current foldback, and wire L/Rs/Psi from FRAM.
…m/saeed95-lab/RTE into feature/fcs-mpcc-three-phase-pmsm
Sanitize Ld/Lq when Config is 0, restore Config.Value on control start, guard EncoderSign≈0, and add mpcc_ld/lq/sign/theta_mech telemetry.
SelfExecutablePath used Linux-only /proc/self/exe; add Apple support and still fall back to PATH when needed.
Unwrap θe derivative spikes, clamp Ωe feedforward, persist non-zero motor/encoder FRAM defaults, harden OC latch, and detune Mode 3 gains.
Raise Mode 3 gains, set I_Max=40 with a higher OC latch threshold, and slow Iq slew for Gen6 bring-up.
Hard OC latch and aggressive gains locked the rotor with huge current; Config repair also treated Sign=-1 as missing and forced +1. Co-authored-by: Cursor <cursoragent@cursor.com>
Session 215141 pinned duties near 50% via an rs-based stall cap (~2 V with Rs≈0.012 Ω) and iq tracked opposite IqVar; match FOC gains/limits and flip q-axis error polarity. Co-authored-by: Cursor <cursoragent@cursor.com>
…m/saeed95-lab/RTE into feature/fcs-mpcc-three-phase-pmsm
Session 220144 still had FRAM Sign=+1 (wrong θe, id ±40 A) and soft foldback that kept duties near 50%; wire Sign=-1 and raise L/Ts current gains. Co-authored-by: Cursor <cursoragent@cursor.com>
…emo) Main fixed the FOC current-dump regression (lost sensor sign inversion in the node-library overhaul) via a configurable InvertPolarity parameter. Port the same template here and enable it on the Currents node so the MPCC loop gets correctly-signed feedback.
Use deadbeat voltage→SVPWM without hard OC foldback, match FOC encoder Sign (+1/FRAM), and document the safe first-spin procedure. Co-authored-by: Cursor <cursoragent@cursor.com>
The graph's embedded Sensors.PhaseCurrents uses the InvertPolarity parameter (ported from main), but the node instance never set it, so codegen emitted no binding and the build failed with 'InvertPolarity was not declared in this scope'.
Lift ωe clamp to ±3000 rad/s, increase deadbeat gain scale to 0.70, and match FOC Iq slew (50 A/s) so 100 V high-speed runs are not starved. Co-authored-by: Cursor <cursoragent@cursor.com>
Fixes optimal-duty FCS-MPCC for synchronous sim, adds bench-motor comparison runner/plots, and keeps this work separate from the prior hardware MPCC branch. Co-authored-by: Cursor <cursoragent@cursor.com>
Softens deadbeat/integral, adds Vdc guards and Iq clamps, retunes mpcc_demo limits/slew, and documents a 50 V quiet bring-up path. Co-authored-by: Cursor <cursoragent@cursor.com>
Rely on I_Max only, raise deadbeat slightly for 50 V tracking, and allow Iq commands up to 15 A in mpcc_demo. Co-authored-by: Cursor <cursoragent@cursor.com>
Add current LPF, clamp Id/Iq refs to I_Max, and prioritize Vq under saturation so mid-bus field-weakening spins more like FOC. Co-authored-by: Cursor <cursoragent@cursor.com>
ESO-assisted modulated FCS-MPCC under Lib/Simulation/hybrid_adrc_mpcc for locked-rotor iq-step review while Gen6 ADRC hardware testing continues. Co-authored-by: Cursor <cursoragent@cursor.com>
New Control.AdrcMpcc node (ESO + mild deadbeat → SVPWM), flashable hybrid_adrc_mpcc_demo graph, and LADRC assets on this branch so colleagues can compare foc_demo, ladrc_demo, and hybrid on the same inverter. Co-authored-by: Cursor <cursoragent@cursor.com>
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Summary
Lib/Simulation/hybrid_adrc_mpcc/Control.AdrcMpccnode +Assets/Examples/hybrid_adrc_mpcc_demo.json(ESO + mild deadbeat → same SVPWM path as MPCC Mode 3 / FOC)ladrc_demo/Control.Ladrcon this branch for FOC vs ADRC vs hybrid comparisonRTECodeEmitterHow to test (hardware)
See
docs/18_hybrid_adrc_mpcc_bringup.md.Compare:
foc_demo.json→ladrc_demo.json→hybrid_adrc_mpcc_demo.json(same iq steps).How to test (sim)
Test plan