Add Gen6 hybrid ADRC+MPCC demo (hardware + sim) - #41
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Provides Control.AdrcMpcc, hybrid_adrc_mpcc_demo graph, bring-up docs, and a standalone locked-rotor hybrid simulation package so colleagues can compare against FOC/LADRC on Gen6 without the larger MPCC experiment history. Co-authored-by: Cursor <cursoragent@cursor.com>
seems to fail compiling, see log:
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The AdrcMpcc header comment used |Id*/Iq*| which terminated the C comment early in generated domain_tim_isr code and broke the STM32 build. Co-authored-by: Cursor <cursoragent@cursor.com>
Replace pure ADRC deadbeat with Mode-3 model feedforward plus mild clamped ESO, add progressive current foldback, and lower bring-up defaults (DbScale=0.20, I_Max=15, OmegaO=1200) after HybridADRCMPC-1 showed ~100 A with almost no sustained rpm. Co-authored-by: Cursor <cursoragent@cursor.com>
HybridADRCMPC-2 showed clean ~2 A currents but duty stuck near 50% and no rotation: DbScale 0.20 with no integrator had almost no voltage authority on low-L Gen6. Reuse the spinning Mode-3 structure (db~0.70, Ki=10, delay compensation) and keep a light clamped ESO residual term. Co-authored-by: Cursor <cursoragent@cursor.com>
The Mode-3 Ki integrators added 8 bytes of DTCM .bss and broke the Gen6 link. Keep AdrcMpcc persistent state in .dma_buffers (RAM_D1) like other large ISR-adjacent buffers. Co-authored-by: Cursor <cursoragent@cursor.com>
.dma_buffers is not zeroed at boot; uninitialized Ki/ESO state produced the HybridADRCMPC-3 300–500 A current spikes. Validate a magic and zero state on first entry. Co-authored-by: Cursor <cursoragent@cursor.com>
Unwrap angle in OmegaDeriv and inside the hybrid ω estimate, hard-clamp overcurrent to zero volts, and drop unused FCS work from the SVPWM path. Co-authored-by: Cursor <cursoragent@cursor.com>
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Current wave form at 50vdc above. |
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Earlier current waveform, very nice |
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Comparison for ladrc at same voltage
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Interpret IqVar as rpm when SpdMode=1, correct ψ≈0.07, ease deadbeat/Iq near the bemf ceiling, and apply mild field-weakening so Gen6 can hold a clean mid-speed spin without the session 5/6 sync-loss blowups. Co-authored-by: Cursor <cursoragent@cursor.com>
SpdMode defaults to 0 so hybrid bring-up matches foc_demo (Iq in A). Speed-loop option remains available but is not the test path. Co-authored-by: Cursor <cursoragent@cursor.com>
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Summary
Control.AdrcMpcc(ESO/ADRC + mild deadbeat → SVPWM) andAssets/Examples/hybrid_adrc_mpcc_demo.jsonfor Gen6 hardware comparison against FOC / LADRC.docs/18_hybrid_adrc_mpcc_bringup.md(safe no-load iq steps, cal params, flash command).Lib/Simulation/hybrid_adrc_mpcc/(./run_hybrid.sh) plus minimal plant headers; does not change the root host-tool CMake graph build path beyond optional Simulation headers.Test plan
cmake -B build -G Ninja && cmake --build build -j8)Assets/Examples/hybrid_adrc_mpcc_demo.jsonvia./Tools/build_flash_graph.shMotor.PMSM.*, enable at iq=0 then ramp iq 1→3 A; confirm no OC and duties leave ~50%Lib/Simulation/hybrid_adrc_mpcc/run_hybrid.shand inspectresults/adrc_mpcc_hybrid/foc_demo/ladrc_demotelemetryMade with Cursor