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Update Router_Hw.scala #1

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ec48ad5
Update Router_Hw.scala
yuliujq Oct 30, 2020
c383c98
Update softbrain.scala
yuliujq Nov 5, 2020
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2 changes: 1 addition & 1 deletion src/main/scala/cgra/fabric/Router_Hw.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ class Router_Hw(pp:(String,Any)) extends Module
for(in<-input_ports;out<-output_ports;subnet<-0 until decomposer){
val in_port_subnet : String = in + "_" + subnet;val col = input_ports_subnet.indexOf(in_port_subnet)
val out_port_subnet : String = out + "_" + subnet;val row = output_ports_subnet.indexOf(out_port_subnet)
IO_LookUpTable(row)(col) = true
IO_LookUpTable(row)(col) = false
}
// Add Intersubnet Connection
for (conn <- inter_subnet_connection){
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4 changes: 2 additions & 2 deletions src/main/scala/real/softbrain.scala
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Expand Up @@ -10,7 +10,7 @@ object softbrain extends App {
val sw_default = new ssnode("switch")

// Define General Function Unit
val fu_general = new ssnode("function unit")
val fu_general = new ssnode("processing element")
fu_general(
"instructions", List("Add", "Sub", "Mul", "FMul64", "FAdd64") )(
"max_delay", 4)
Expand Down Expand Up @@ -54,7 +54,7 @@ object softbrain extends App {
softbrain(in_vport2 |=> softbrain.filter("col_idx","nodeType")(0,"switch"))
softbrain(out_vport <=| softbrain.filter("row_idx","nodeType")(4,"switch"))

in_vport1 |=> List(sw_default, sw_default, sw_default)
//in_vport1 |=> List(sw_default, sw_default, sw_default)

// Print
softbrain.printIR
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