QEMU CPU Test Matrix

QEMU CPU Test Matrix

Purpose

This page defines the QEMU CPU models XAI OS should test against before moving from QEMU correctness work to hardware-specific ports.

QEMU CPU testing is for boot, feature-detection, exception, memory-management, userspace, driver, and telemetry correctness. It is not a hardware performance benchmark and must not be used for Linux, BSD, Intel, ARM, NVIDIA, or Apple Silicon speedup claims.

Implementation work for these CPU profiles starts after the full OS completion milestones in Project Tracker.

Contents

• Host QEMU Baseline
• Testing Policy
• ARM64 CPU Matrix
• x86_64 Desktop CPU Matrix
• x86_64 Server CPU Matrix
• x86_64 AMD CPU Matrix
• Unsupported Requested Models
• Recommended Gate Tiers
• Command Examples
• Related Pages

Host QEMU Baseline

Current local toolchain checked on the Apple Silicon development host:

Tool	Path	Version
qemu-system-aarch64	/opt/homebrew/bin/qemu-system-aarch64	QEMU 11.0.1
qemu-system-x86_64	/opt/homebrew/bin/qemu-system-x86_64	QEMU 11.0.1

Apple Silicon can use AArch64 QEMU with HVF for fast local correctness testing. x86_64 QEMU on Apple Silicon uses emulation and is useful for compatibility and boot-shape testing only.

Important accelerator distinction:

• AArch64 HVF on this host accepts only a small CPU set: host, max, cortex-a53, and cortex-a57.
• Most named ARM CPU models listed by qemu-system-aarch64 -cpu help require XAIOS_QEMU_ACCEL=tcg.
• The fast local smoke target should therefore use host with HVF.
• The broader ARM64 compatibility matrix should use TCG.

Testing Policy

• Keep host with HVF as the fast local ARM64 smoke target on Apple Silicon.
• Keep cortex-a72 with TCG as the portable ARM64 default when host-specific behavior should be avoided.
• Use max to expose the broadest QEMU-supported feature set for future-proof correctness testing.
• Use named Intel server/client models to prepare feature-detection code paths before real hardware work.
• Treat all QEMU results as correctness evidence only.
• Do not use QEMU CPU timing as performance evidence.

ARM64 CPU Matrix

CPU model	Supported by local QEMU	Accelerator	XAI OS role	Notes
host	yes	HVF	Fast Apple Silicon local smoke target	Uses host CPU exposure with HVF where available.
cortex-a53	yes	HVF or TCG	Weak ARMv8 baseline	Good for minimum architectural compatibility.
cortex-a72	yes	TCG	Portable default ARM64 target	Common ARMv8 profile and current fallback default.
cortex-a76	yes	TCG	Modern ARM compatibility target	Useful before Neoverse-specific testing.
cortex-a710	yes	TCG	Newer client/mobile-class ARM target	Useful for ARMv9-style compatibility checks.
neoverse-n1	yes	TCG	ARM server baseline	Good Graviton2-class compatibility approximation.
neoverse-n2	yes	TCG	Modern ARM server target	Best local substitute for some newer server-class ARM behavior.
neoverse-v1	yes	TCG	High-performance ARM server target	Useful for high-end ARM server feature paths.
max	yes	HVF or TCG	Broad feature exposure target	Useful to catch feature-detection assumptions.

Initial ARM64 QEMU gate targets:

1. host
2. cortex-a53
3. cortex-a72
4. cortex-a76
5. cortex-a710
6. neoverse-n1
7. neoverse-n2
8. neoverse-v1
9. max

x86_64 Desktop CPU Matrix

XAI OS should not spend QEMU gate coverage on Intel desktop models older than Skylake. The local QEMU build exposes older models such as Broadwell, Haswell, IvyBridge, and SandyBridge, but they are intentionally excluded from the recommended matrix.

CPU model	Supported by local QEMU	XAI OS role	Notes
Skylake-Client	yes	Conservative Intel Desktop compatibility	Good first client-class x86_64 profile.
AlderLake	no	Intended Intel Desktop hardware profile	Use an XAI OS compatibility profile until QEMU gains native support.
max	yes	Broad x86_64 feature exposure target	QEMU exposes all features supported by the current accelerator.

Recommended QEMU desktop profile mapping:

XAI OS profile	QEMU CPU model	Reason
intel-desktop-conservative	Skylake-Client	Stable baseline for x86_64 client boot paths.
intel-desktop-alderlake-compat	max	Best available local compatibility stand-in for Alder Lake-style feature exposure.

The intel-desktop-alderlake-compat profile is not a real Alder Lake emulation model. Real Alder Lake support must be validated on physical Intel Desktop hardware later.

x86_64 Server CPU Matrix

XAI OS server-class QEMU testing should focus on Intel server CPUs from Skylake onward.

CPU model	Supported by local QEMU	XAI OS role	Notes
Skylake-Server	yes	Conservative Xeon baseline	Good first server-class boot and feature-detection target.
Cascadelake-Server	yes	Post-Skylake Xeon target	Useful for ARCH_CAPABILITIES and no-TSX variants.
Cooperlake	yes	Xeon compatibility target	Useful for XSAVES and server feature coverage.
Icelake-Server	yes	Modern Xeon baseline	Useful for newer server feature paths and 5-level paging planning.
SapphireRapids	yes	Current high-end Xeon target	Important for AMX/vector-policy planning.
GraniteRapids	yes	Future Xeon target	Useful for forward compatibility.
DiamondRapids	yes	Future Xeon target	Useful for very new Intel server feature detection.
SierraForest	yes	Xeon E-core server target	Useful for dense-core server policy planning.
ClearwaterForest	yes	Newer Xeon E-core server target	Useful for forward dense-core compatibility.
Denverton	yes	Intel Atom server-edge target	Lower-power server/edge profile newer than Skylake.
Snowridge	yes	Intel Atom server-edge target	Server/edge networking profile newer than Skylake.
max	yes	Broad x86_64 feature exposure target	Useful for feature-detection stress testing.

x86_64 AMD CPU Matrix

XAI OS should also track AMD EPYC models from the same general era as Intel Skylake and newer. These are QEMU correctness profiles only, not AMD hardware performance targets yet.

CPU model	Supported by local QEMU	XAI OS role	Notes
EPYC	yes	First-generation AMD EPYC baseline	Useful for Zen-era server compatibility.
EPYC-Rome	yes	AMD EPYC Rome target	Useful for Zen 2 server compatibility.
EPYC-Milan	yes	AMD EPYC Milan target	Useful for Zen 3 server compatibility.
EPYC-Genoa	yes	AMD EPYC Genoa target	Useful for Zen 4 server compatibility.
EPYC-Turin	yes	AMD EPYC Turin target	Useful for newer AMD server compatibility.

The local QEMU build does not expose named Ryzen desktop CPU models. If AMD desktop support becomes a target, use max for QEMU compatibility checks and validate real behavior on physical AMD hardware later.

Unsupported Requested Models

Requested model	Status	Practical substitute
neoverse-v2	Not listed by local QEMU 11.0.1	neoverse-n2, neoverse-v1, or max
AlderLake	Not listed by local QEMU 11.0.1	max for compatibility exposure, Skylake-Client for conservative client baseline
RaptorLake	Not listed by local QEMU 11.0.1	max for compatibility exposure, physical hardware later
RocketLake	Not listed by local QEMU 11.0.1	max for compatibility exposure, physical hardware later
TigerLake	Not listed by local QEMU 11.0.1	max for compatibility exposure, physical hardware later
MeteorLake	Not listed by local QEMU 11.0.1	max for compatibility exposure, physical hardware later
ArrowLake	Not listed by local QEMU 11.0.1	max for compatibility exposure, physical hardware later

Unsupported QEMU models should not block XAI OS planning. They should become named XAI OS platform profiles with explicit substitute QEMU models and later physical-hardware validation requirements.

Recommended Gate Tiers

Tier	Purpose	CPU models
Fast local smoke	Run frequently during QEMU development	host with HVF, optionally max with HVF
ARM64 compatibility	Validate AArch64 boot and kernel assumptions	cortex-a53, cortex-a72, cortex-a76, cortex-a710, neoverse-n1, neoverse-n2, neoverse-v1, max with TCG
Intel x86_64 compatibility	Prepare non-performance Intel x86_64 boot path work	Skylake-Client, Skylake-Server, Cascadelake-Server, Cooperlake, Icelake-Server, SapphireRapids, GraniteRapids, DiamondRapids, SierraForest, ClearwaterForest, Denverton, Snowridge, max
AMD x86_64 compatibility	Prepare non-performance AMD x86_64 boot path work	EPYC, EPYC-Rome, EPYC-Milan, EPYC-Genoa, EPYC-Turin
Release gate	Run before declaring a QEMU readiness milestone	ARM64 compatibility plus x86_64 smoke-boot checks

The implemented QEMU release-candidate gate records these tiers in build/qemu-cpu-matrix-report.json.

ARM64 alternate CPU tiers use a boot probe that must reach kernel start, SMP, VMM, VirtIO block, and persistence markers. The full userspace, networking, AI Cell, CPU-AI runtime, security, and telemetry smoke path remains covered by the default host/HVF QEMU smoke gate. x86_64 tiers must reach the Intel Desktop milestone 43-51 smoke markers for each supported CPU model or compatibility substitute.

Command Examples

ARM64 examples:

XAIOS_QEMU_CPU=host make qemu-smoke
XAIOS_QEMU_CPU=max make qemu-smoke
XAIOS_QEMU_ACCEL=tcg XAIOS_QEMU_CPU=cortex-a53 make qemu-smoke
XAIOS_QEMU_ACCEL=tcg XAIOS_QEMU_CPU=cortex-a72 make qemu-smoke
XAIOS_QEMU_ACCEL=tcg XAIOS_QEMU_CPU=cortex-a76 make qemu-smoke
XAIOS_QEMU_ACCEL=tcg XAIOS_QEMU_CPU=cortex-a710 make qemu-smoke
XAIOS_QEMU_ACCEL=tcg XAIOS_QEMU_CPU=neoverse-n1 make qemu-smoke
XAIOS_QEMU_ACCEL=tcg XAIOS_QEMU_CPU=neoverse-n2 make qemu-smoke
XAIOS_QEMU_ACCEL=tcg XAIOS_QEMU_CPU=neoverse-v1 make qemu-smoke
XAIOS_QEMU_ACCEL=tcg XAIOS_QEMU_CPU=max make qemu-smoke

x86_64 smoke examples:

XAIOS_QEMU_X86_CPU=Skylake-Client make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=Skylake-Server make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=Cascadelake-Server make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=Cooperlake make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=Icelake-Server make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=SapphireRapids make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=GraniteRapids make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=DiamondRapids make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=SierraForest make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=ClearwaterForest make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=Denverton make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=Snowridge make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=EPYC make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=EPYC-Rome make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=EPYC-Milan make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=EPYC-Genoa make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=EPYC-Turin make qemu-x86_64-smoke
XAIOS_QEMU_X86_CPU=max make qemu-x86_64-smoke

The x86_64 commands validate CPU-model availability and the milestone 43-51 QEMU smoke boot path. They do not prove physical hardware behavior or performance.

Related Pages

• QEMU on macOS
• Project Tracker
• Hardware Readiness Gate
• Intel Desktop Port
• Intel Xeon Port
• ARM NVIDIA Port
• Testing and Benchmarking