fix(cpu): ARMv6-M exception priority model — stop GPIO IRQ self-preemption#53
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…ption CheckForInterrupts took any pending+enabled exception with no notion of execution priority. A level-held IRQ like IO_IRQ_BANK0 (re-asserted by IoBank0 until the handler acks INTR) therefore re-preempted its own handler after every instruction; the stack unwound into RAM and the core died in a HardFault lockup loop the moment a MicroPython Pin.irq handler saw its first edge. Implement the ARMv6-M (B1.5.4) model: - NVIC IPR levels live in four per-level bitmask buckets, rebuilt on IPR writes (2-bit priorities in bits 7:6 of each byte); reset puts every IRQ at level 0. - Execution priority derives from IPSR (NMI=-2, HardFault=-1, SVCall/ PendSV/SysTick from SHPR2/3, IRQs from their bucket); PRIMASK boosts it to 0. SHPR2/3 writes are masked to their implemented bits. - A pending exception preempts only when strictly more urgent; ties resolve to the lowest exception number, matching NVIC arbitration. - MSR PRIMASK re-arms the interrupt check so unmasking takes effect immediately. Regression-tested with MicroPython v1.21: Pin.irq callbacks now count externally forced edges and a 50-edge burst leaves the REPL responsive. Claude-Session: https://claude.ai/code/session_01LzMZxpFZefZTzGPCfg2AHq
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Corrects the ARMv6-M exception priority/preemption model in the Cortex-M0+ core (CortexM0Plus, SystemOps, PpbPeripheral) so a GPIO IRQ no longer self-preempts. Adds MicroPythonGpioIrqTests.
Verified: unit 516/0, new GPIO IRQ integration test 2/0. Ships as 1.0.1-beta.11.
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