fix(pwm): implement CSR.DIVMODE — B-pin gated and edge-count modes#55
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The PWM slices always advanced at clk_sys/DIV, ignoring DIVMODE, and the B pins had no input path into the peripheral. CircuitPython's countio — which programs DIVMODE=rising-edge on a B pin — therefore counted clock cycles instead of edges (253M "edges" in 4 s of a 4 Hz square wave). IoBank0 now fans out pad-input transitions (OnInputChanged) and the machine routes odd GPIOs muxed to PWM (FUNCSEL 4) into their slice's SetBInput, which drives the gated (count while B high) and rising/falling edge-count modes. Free-running slices behave exactly as before. Verified: 5 new DIVMODE unit tests; suites 521/0 unit + 162/0 integration; E2E in-circuit CircuitPython countio on GP17 counts 16/16 rising edges of a 4 Hz rail. Claude-Session: https://claude.ai/code/session_01LzMZxpFZefZTzGPCfg2AHq
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Implements PWM
CSR.DIVMODE(B-pin gated and edge-count modes). Verified: unit 521/0. First stable BUSL release: 1.0.1.