$ system_info --fetch FOCUS: ASIC Design, RTL-to-GDSII Flow, AI Hardware LANGUAGES: SystemVerilog, Verilog, C/C++, Python SCRIPTING: TCL, Perl, Bash BUILDING: RISC-V Architecture & Edge AI Accelerators HONORS: Samsung Fellowship (Grade II) MAJOR: B.Tech Electronics Eng (VLSI) | CGPA: 8.84 COLLEGE: Vellore Institute of Technology |
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[root@R_NAGA_ARJUN ~]# ./display_workflow.sh _________________________________________________________________________ | | | [1] RTL DESIGN & ARCHITECTURE [2] ASIC FLOW & AUTOMATION | | -> SystemVerilog, Verilog -> RTL to GDSII Flow | | -> RISC-V Microarchitecture -> TCL & Perl Scripting | | -> AI/ML Hardware Accelerators -> Standard Cell Methodology | | | | [3] VERIFICATION & TEST [4] ALGORITHMS & PROTOTYPING | | -> Verilator, DPI-C -> Python, C++, LeetCode | | -> Hardware Assertions -> Data Structures & Logic | |_________________________________________________________________________|
| Role / Project | Description | Highlights |
|---|---|---|
| VLSI Research Intern CNVD, VIT |
VLSI implementation of Convolutional Neural Networks (CNNs). | Focused on neuromorphic computing and hardware-accelerated Edge AI via CrossSim. |
| GaN HEMT | Novel innovation related to source-connected field plates for 650V GaN-on-Si HEMTs. | Extensive TCAD device modeling focusing on reliability optimization for EV fast charging. |
| RISC-V Trace Encoder | Cycle-accurate hardware trace encoder development. | Deepened expertise in open-source silicon and cycle-accurate verification. |
| BlackParrot Core | Open-source contribution to a Linux-capable, cache-coherent, RV64G multicore processor. | Implemented and verified hardware safety assertions. |