LFSR Lunetta Sound Generator

A 32-stage linear-feedback shift register (LFSR) sound generator on a Tiny Tapeout tile, fabricated on the open SKY130 process. It is the custom-silicon stage of an ongoing project on CPU-free hardware synthesis and multichannel spatialization with LFSRs; the concept, theory, and demonstrations are documented in SCLW/hardware-lfsr.

The chip reimplements, in real silicon, the architecture first built from off-the-shelf logic chips (a CD4094 shift register, XOR/XNOR feedback, and ADG732 multiplexers): pseudo-random bit streams whose clock rate and feedback taps shape both the sound and its distribution across loudspeakers, all driven by parallel logic inputs rather than a CPU.

What it does

A 32-stage Fibonacci LFSR generates a pseudo-random bit stream that is sent raw, as square pulses, to the output pins.

• Pitch. A clock divider (RATE, divide by up to roughly 2^15) sets the LFSR step rate.
• Timbre (MUX A). Each step shifts in the XOR of stage 32 and a second tap chosen by an on-chip 32:1 multiplexer (FB_SEL, five parallel select lines, the silicon equivalent of an ADG732). The tap choice sets the sequence length, from maximum-length pseudo-noise down to short tonal loops.
• Output channel (MUX B). A second 32:1 multiplexer (OUT_SEL) picks which register stage drives the main audio output, MUX_OUT.
• Lock-up elimination. A de Bruijn modification (a NOR across stages 1 to 31 inverts the feedback at the right moment) makes the all-zero state a legal step, giving the full 2^32 sequence length and self-seeding the register after reset.
• Multichannel taps. Stages 4, 8, 12, 16, 20, 24, and 28 are brought out in parallel on TAP4..TAP28: seven phase-shifted copies of the sequence for distribution around a loudspeaker ring.
• Modulator / LFO. A second 8-stage LFSR (maximal taps 8, 6, 5, 4) acts as an on-chip LFO. With FREEZE and INJECT both high (MOD mode), the FB_SEL switches become a small routing matrix that patches the LFO to the rhythm gate, the output channel, or the feedback tap, for pseudo-random stutter, channel hopping, and timbral mutation.

FREEZE and INJECT select four modes: normal (free-running), freeze (feedback off, the stored bits rotate as a loop), inject (feedback forced high, manual disturb or re-seed), and MOD (the LFO routing matrix above).

Design

• src/lfsr32.v — 32-stage LFSR core with MUX A (feedback-tap select) and de Bruijn lock-up elimination
• src/lfsr8.v — 8-stage modulator LFSR (the LFO)
• src/clkdiv.v — clock divider (pitch)
• src/project.v — top wrapper (tt_um_sclw_lfsr32): MUX B, mode logic, and pin mapping

Full datasheet, pinout, and mode tables: docs/info.md.

Pinout

Inputs ui	Bidirectional uio	Outputs uo
FB_SEL0..4 (MUX A tap)	OUT_SEL0..4 (MUX B channel)	TAP4..TAP28 (7 phase-shifted taps)
RATE0..2 (pitch)	FREEZE, INJECT, RATE3	MUX_OUT (selected bit to audio)

Testing

A cocotb testbench (test/, run with cd test && make using Icarus Verilog) checks the bit stream against a golden software model, along with the divider, both multiplexers, lock-up elimination, and freeze mode.

For audio, clock the design in the few-hundred-kHz to few-MHz range and divide down with RATE. After reset the LFSR self-seeds; listen on MUX_OUT (the TT Audio Pmod position), or connect several TAP pins to separate speakers for the multichannel effect.

Fabrication

Hardened with the open-source LibreLane flow on the SKY130 PDK and submitted through Tiny Tapeout. One 1x1 tile.

License

Apache-2.0 (see the SPDX headers in src/). Copyright (c) 2026 Lorenz Schwarz.