ENH: Fast TDL TDC

[MarcoVogt]

TDC implementation with sub-ns resolution based on tapped delay lines (TDL).

[cbespin]

@MarcoVogt I took some of these commits and made them their own PR, especially since #230 already existed. Maybe rebase (or merge) before you continue coding to prevent ugly merge conflicts later

[cbespin]

Thanks! I will give this a review as soon as possible! There are currently no tests covering any of the tdl_tdc, right?

[codecov]

Codecov Report

Attention: Patch coverage is 1.12360% with 88 lines in your changes missing coverage. Please review.

Project coverage is 13.98%. Comparing base (4480251) to head (0803dfc).
Report is 34 commits behind head on master.

Files with missing lines	Patch %	Lines
basil/HL/tdl_tdc.py	0.00%	88 Missing ⚠️

❗ There is a different number of reports uploaded between BASE (4480251) and HEAD (0803dfc). Click for more details.

HEAD has 1 upload less than BASE

Flag	BASE (4480251)	HEAD (0803dfc)
	2	1

Additional details and impacted files

@@             Coverage Diff             @@
##           master     #231       +/-   ##
===========================================
- Coverage   31.48%   13.98%   -17.51%     
===========================================
  Files          87       88        +1     
  Lines        6026     6123       +97     
===========================================
- Hits         1897      856     -1041     
- Misses       4129     5267     +1138     

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[cbespin]

@MarcoVogt I am currently implementing this in a full-fledged FPGA firmware and wondering: why are the timestamps only 16bit. According to the readme, in all occurrences where they are written, they are padded with 9bits of 0s that one could use for more timestamp bits. This would help with correlating TDC words to pixel hit information.
Or am I not seeing a showstopper to extend the timestamp to 25 bits?