Fix bit_width calculation for ascending bus ranges in writeBusDcls

[JayPankajPatel]

Summary

Fixes #360.

writeBusDcls() in liberty/LibertyWriter.cc computes bit_width incorrectly for ascending bus ranges (e.g. [0:10]).

Root Cause

// before — +1 inside abs(), wrong for ascending ranges
std::abs(dcl->from() - dcl->to() + 1)
// ascending  [0:10]:  abs(0  - 10 + 1) = abs(-9) = 9   ← WRONG
// descending [10:0]:  abs(10 - 0  + 1) = 11             ← correct

// after — +1 outside abs(), correct for both
std::abs(dcl->from() - dcl->to()) + 1
// ascending  [0:10]:  abs(0  - 10) + 1 = 11  ✓
// descending [10:0]:  abs(10 - 0)  + 1 = 11  ✓

Change

One character moved — +1 from inside std::abs() to outside.

Impact

Ascending bus ranges are generated by OpenFPGA throughout its RTL output. Without this fix, write_timing_model produces Liberty files with incorrect bit_width values that Yosys rejects:

ERROR: Incompatible array type 'chanx_left_in': bit_width=9, bit_from=0, bit_to=10.

This blocks top-level macro assembly in OpenLane when using EXTRA_LIBS with OpenFPGA-generated designs on sky130A.

Verification

Reproducer and confirmation that the fix resolves it is attached to issue #360.

Tested against OpenSTA 2.5.0.

[CLAassistant]

All committers have signed the CLA.

[gemini-code-assist]

Code Review

This pull request corrects the bit width calculation for bus declarations in LibertyWriter.cc by moving the increment outside the absolute difference of the range bounds. Feedback suggests adding regression tests for both ascending and descending bus ranges to ensure continued correctness, as the existing test suite does not currently verify bus declaration content.

[gemini-code-assist]

While the logic change correctly addresses the bit width calculation for ascending bus ranges, it is highly recommended to include a regression test case in liberty/test/liberty_writer.tcl (or a new test file) that specifically verifies both ascending (e.g., [0:10]) and descending (e.g., [10:0]) bus ranges. The current test suite does not appear to verify the content of bus declarations, which could lead to similar regressions in the future.