RISCV

RISCV_implementation/.project

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+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>Scrolling_8x8</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<filteredResources>
+		<filter>
+			<id>1595986042669</id>
+			<name></name>
+			<type>22</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*.wvproj</arguments>
+			</matcher>
+		</filter>
+	</filteredResources>
+</projectDescription>

RISCV_implementation/.settings/language.settings.xml

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+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="997885723315898399" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

RISCV_implementation/.settings/org.eclipse.core.resources.prefs

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+eclipse.preferences.version=1
+encoding//User/ch32v003fun/ch32v003_i2c.h=GBK
+encoding//User/ch32v003fun/ch32v003fun.c=GBK
+encoding//User/ch32v003fun/ch32v003fun.h=UTF-8
+encoding//User/ch32v003fun/driver.h=GBK
+encoding//User/ch32v003fun/oled_min.c=GBK
+encoding//User/ch32v003fun/ws2812b_simple.h=GBK
+encoding//User/ch32v00x_conf.h=GBK
+encoding//User/data/Clean_code_func/colors_predefined.h=GBK
+encoding//User/data/Clean_code_func/fonts8x8.h=GBK
+encoding//User/data/colors.h=GBK
+encoding//User/data/fonts.h=GBK
+encoding//User/data/music.h=GBK
+encoding//User/funconfig.h=GBK
+encoding//User/main.c=GBK
+encoding//obj/InspireRV3.map=GBK
+encoding//obj/Snake_game.map=GBK

RISCV_implementation/.template

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+Vendor=WCH
+Toolchain=RISC-V
+Series=CH32V003
+RTOS=NoneOS
+MCU=CH32V003F4P6
+Link=WCH-Link
+PeripheralVersion==1.9
+Description==Website: https://www.wch.cn/products/CH32V003.html?\nThe CH32V003 series is an industral-grade general-purpose microcontroller designed based on the highland barley RISCV-V2A core, and supports 48MHz system frequency in terms of product functions. This series has the characteristics of wide voltage, single-wire debugging, low power consumption, ultra-small package and so on. Provide common peripheral functions, built-in 1 set of DMA controller, 1 set of 10-bit analog-to-digital conversion ADC, 1 set of op amp comparator, multiple sets of timers, standard communication interfaces such as USART, I2C, SPI, etc. The rated working voltage of the product is 3.3V or 5V, and the working temperature range is -40'C~85'C industrial grade.
+Mcu Type=CH32V00x
+Address=0x08000000
+CLKSpeed=1
+DebugInterfaceMode=-1
+Erase All=true
+Program=true
+Verify=true
+Reset=true
+SDIPrintf=false
+Target Path=obj/Scrolling_8x8.hex

RISCV_implementation/Core/core_riscv.c

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+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : core_riscv.c
+ * Author             : WCH
+ * Version            : V1.0.1
+ * Date               : 2023/11/11
+ * Description        : RISC-V V2 Core Peripheral Access Layer Source File for CH32V003
+ *********************************************************************************
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * Attention: This software (modified or not) and binary are used for 
+ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
+ *******************************************************************************/
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined(__CC_ARM)
+  #define __ASM       __asm     /*!< asm keyword for ARM Compiler          */
+  #define __INLINE    __inline  /*!< inline keyword for ARM Compiler       */
+
+#elif defined(__ICCARM__)
+  #define __ASM       __asm   /*!< asm keyword for IAR Compiler          */
+  #define __INLINE    inline  /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined(__GNUC__)
+  #define __ASM       __asm   /*!< asm keyword for GNU Compiler          */
+  #define __INLINE    inline  /*!< inline keyword for GNU Compiler       */
+
+#elif defined(__TASKING__)
+  #define __ASM       __asm   /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE    inline  /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+/*********************************************************************
+ * @fn      __get_MSTATUS
+ *
+ * @brief   Return the Machine Status Register
+ *
+ * @return  mstatus value
+ */
+uint32_t __get_MSTATUS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mstatus": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MSTATUS
+ *
+ * @brief   Set the Machine Status Register
+ *
+ * @param   value  - set mstatus value
+ *
+ * @return  none
+ */
+void __set_MSTATUS(uint32_t value)
+{
+    __ASM volatile("csrw mstatus, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MISA
+ *
+ * @brief   Return the Machine ISA Register
+ *
+ * @return  misa value
+ */
+uint32_t __get_MISA(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""misa" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MISA
+ *
+ * @brief   Set the Machine ISA Register
+ *
+ * @param   value - set misa value
+ *
+ * @return  none
+ */
+void __set_MISA(uint32_t value)
+{
+    __ASM volatile("csrw misa, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MTVEC
+ *
+ * @brief   Return the Machine Trap-Vector Base-Address Register
+ *
+ * @return  mtvec value
+ */
+uint32_t __get_MTVEC(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mtvec": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVEC
+ *
+ * @brief   Set the Machine Trap-Vector Base-Address Register
+ *
+ * @param   value  - set mtvec value
+ *
+ * @return  none
+ */
+void __set_MTVEC(uint32_t value)
+{
+    __ASM volatile("csrw mtvec, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MSCRATCH
+ *
+ * @brief   Return the Machine Seratch Register
+ *
+ * @return  mscratch value
+ */
+uint32_t __get_MSCRATCH(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mscratch" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MSCRATCH
+ *
+ * @brief   Set the Machine Seratch Register
+ *
+ * @param   value  - set mscratch value
+ *
+ * @return  none
+ */
+void __set_MSCRATCH(uint32_t value)
+{
+    __ASM volatile("csrw mscratch, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MEPC
+ *
+ * @brief   Return the Machine Exception Program Register
+ *
+ * @return  mepc value
+ */
+uint32_t __get_MEPC(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mepc" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MEPC
+ *
+ * @brief   Set the Machine Exception Program Register
+ *
+ * @return  mepc value
+ */
+void __set_MEPC(uint32_t value)
+{
+    __ASM volatile("csrw mepc, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MCAUSE
+ *
+ * @brief   Return the Machine Cause Register
+ *
+ * @return  mcause value
+ */
+uint32_t __get_MCAUSE(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mcause": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MEPC
+ *
+ * @brief   Set the Machine Cause Register
+ *
+ * @return  mcause value
+ */
+void __set_MCAUSE(uint32_t value)
+{
+    __ASM volatile("csrw mcause, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MVENDORID
+ *
+ * @brief   Return Vendor ID Register
+ *
+ * @return  mvendorid value
+ */
+uint32_t __get_MVENDORID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""mvendorid": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MARCHID
+ *
+ * @brief   Return Machine Architecture ID Register
+ *
+ * @return  marchid value
+ */
+uint32_t __get_MARCHID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""marchid": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MIMPID
+ *
+ * @brief   Return Machine Implementation ID Register
+ *
+ * @return  mimpid value
+ */
+uint32_t __get_MIMPID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""mimpid": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MHARTID
+ *
+ * @brief   Return Hart ID Register
+ *
+ * @return  mhartid value
+ */
+uint32_t __get_MHARTID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""mhartid": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_SP
+ *
+ * @brief   Return SP Register
+ *
+ * @return  SP value
+ */
+uint32_t __get_SP(void)
+{
+    uint32_t result;
+
+    __ASM volatile("mv %0,""sp": "=r"(result):);
+    return (result);
+}