Feature/pcie #39
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Feature/pcie #39
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…names with VHDL-2019 bit types
…es with UpperCamelCase naming
…gned types with UpperCamelCase naming" This reverts commit 7f3e477.
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The PCIe v4 VHDL implementation includes a common package defining link widths and Gen1–Gen4 speeds, TLP and DLLP types, flow control, LTSSM and power states, along with a core package providing transaction-layer interfaces and PHY lane definitions.
It aligns with AXI4/Avalon interface patterns, and resolves issue #20 as part of the High-Speed Serial Interfaces milestone.