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Fix RISC-V JALR lift when rs1==rd #6213

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Merged
emesare merged 1 commit into from
Dec 1, 2024
Merged

Fix RISC-V JALR lift when rs1==rd #6213

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4 changes: 3 additions & 1 deletion arch/riscv/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -1242,14 +1242,16 @@ impl<D: 'static + RiscVDisassembler + Send + Sync> architecture::Architecture fo
(1, _, _) => il.call(target).append(), // indirect call
(0, _, _) => il.jump(target).append(), // indirect jump
(_, _, _) => {
// store the target in a temporary register so we don't clobber it when rd == rs1
il.set_reg(max_width, llil::Register::Temp(0), target).append();
// indirect jump with storage of next address to non-`ra` register
il.set_reg(
max_width,
Register::from(rd),
il.const_ptr(addr.wrapping_add(inst_len)),
)
.append();
il.jump(target).append();
il.jump(il.reg(max_width, llil::Register::Temp(0))).append();
}
}
}
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