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Support parsing ordering immediate for i32.atomic.load - #5

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stevenfontanella merged 3 commits into
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i32load
Jul 30, 2026
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Support parsing ordering immediate for i32.atomic.load#5
stevenfontanella merged 3 commits into
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i32load

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@stevenfontanella stevenfontanella commented Jul 30, 2026

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  • Copy over spec test generation script from Binaryen, with some changes, e.g. most cases commented except for i32.atomic.load.
  • Add text parsing support for the ordering immediate on i32.atomic.load.

Once the approach looks good, I'll continue with printing support, binary encoding and decoding, and the remaining instructions.

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stevenfontanella marked this pull request as draft July 30, 2026 01:10
@stevenfontanella stevenfontanella changed the title I32load Acqrel ordering for i32.atomic.load Jul 30, 2026
@stevenfontanella stevenfontanella changed the title Acqrel ordering for i32.atomic.load Support ordering immediate for i32.atomic.load Jul 30, 2026
@stevenfontanella stevenfontanella changed the title Support ordering immediate for i32.atomic.load Support parsing ordering immediate for i32.atomic.load Jul 30, 2026
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stevenfontanella force-pushed the i32load branch 3 times, most recently from fa987e2 to 80ae2e8 Compare July 30, 2026 18:51
tlively pushed a commit to WebAssembly/threads that referenced this pull request Jul 30, 2026
For use in the [relaxed atomics proposal](https://github.com/WebAssembly/relaxed-atomics), e.g. WebAssembly/relaxed-atomics#5 (based on top of this PR). This allows us to introduce more orderings (e.g. acqrel, and potentially others) to atomic instructions.

Keeping the ordering in the `memop` record allows us to avoid introducing a second `atomicmemop` record and duplicating several functions that use `memop` e.g. in [decode.ml](https://github.com/WebAssembly/threads/blob/979d0fcb994439423d63b2f0a8a7332d6285dd84/interpreter/binary/decode.ml#L223), [encode.ml](https://github.com/WebAssembly/threads/blob/979d0fcb994439423d63b2f0a8a7332d6285dd84/interpreter/binary/encode.ml#L149), [arrange.ml](https://github.com/WebAssembly/threads/blob/979d0fcb994439423d63b2f0a8a7332d6285dd84/interpreter/text/arrange.ml#L401-L409), and [valid.ml](https://github.com/WebAssembly/threads/blob/979d0fcb994439423d63b2f0a8a7332d6285dd84/interpreter/valid/valid.ml#L194).
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stevenfontanella marked this pull request as ready for review July 30, 2026 20:55
i32_atomic_load (opt a 2) o ordering)
| "i64.atomic.load" ->
ATOMIC_LOAD (fun a o ->
ATOMIC_LOAD (fun a o ordering ->

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Not sure if you intentionally add ordering to i64.atomic.load here or not. Since you are going to update other instructions in follow-up PRs, it is okay to leave it like this probably.

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It's intentional because the ATOMIC_LOAD lexeme got the extra ordering argument which needs to be included here:

%token<int option -> Memory.offset -> Ast.ordering -> Ast.instr'> ATOMIC_LOAD
. But the complete support still isn't there for i64.atomic.load because i64_atomic_load doesn't take the argument and is hardcoded to use SeqCst instead:
let i64_atomic_load align offset =
AtomicLoad {ty = I64Type; align; offset; pack = None; ordering = SeqCst}
.

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Got it. That makes sense.

ATOMIC_STORE (fun a o ->
(i64_atomic_store (opt a 3)) o)
| "i32.atomic.load8_u" ->
ATOMIC_STORE (fun a o ->

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Unrelated to this PR, but I noticed usage of ATOMIC_STORE for some of the load instructions such as i32.atomic.load8_u and the 4 instructions below. Is this a mistake or there is an explanation for that?

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Interesting, that does seem like a typo. Will look at this separately.

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If this does cause other atomic loads to be parsed as stores, then I would hope there are tests that fail because of it.

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It was introduced here. ATOMIC_LOAD and ATOMIC_STORE are both tokens with the same signature (at least until this PR): https://github.com/WebAssembly/threads/blob/cc535ada1aa21cfaa3cabf3ac73b89acef78a0a0/interpreter/text/parser.mly#L222, so it turns out they're actually indistinguishable. They don't correspond to text since that's done on the LHS of the token parser: https://github.com/WebAssembly/threads/blob/cc535ada1aa21cfaa3cabf3ac73b89acef78a0a0/interpreter/text/lexer.mll#L267.

So there's no real bug, it's just confusing code. Arguably ATOMIC_LOAD and ATOMIC_STORE could be folded into one token (ATOMIC_MEMORY_OP?) and ditto for similar instructions like LOAD and STORE, but the naming might end up more confusing. I'll send a PR to the threads repo.

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And FWIW I verified this by round-tripping a i32.atomic.load8_u instruction with ./interpreter/wasm test/core/relaxed-atomics/relaxed-atomics.wast -o out.wast which gave back the same instruction.

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Approach looks good to me (FWIW)

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stevenfontanella merged commit a3615c6 into main Jul 30, 2026
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3 participants