fix some issues for missunit

scripts/icache_related/icache_missunit_internals.yaml

@@ -1,76 +1,31 @@
 ICacheMissUnit:
   - "wire _prefetchMSHRs_9_io_req_ready"
   - "wire _prefetchMSHRs_9_io_acquire_valid"
-  - "wire [41:0] _prefetchMSHRs_9_io_resp_bits_blkPaddr"
-  - "wire [7:0] _prefetchMSHRs_9_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_8_io_req_ready"
   - "wire _prefetchMSHRs_8_io_acquire_valid"
-  - "wire [41:0] _prefetchMSHRs_8_io_resp_bits_blkPaddr"
-  - "wire [7:0] _prefetchMSHRs_8_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_7_io_req_ready"
   - "wire _prefetchMSHRs_7_io_acquire_valid"
-  - "wire [41:0] _prefetchMSHRs_7_io_resp_bits_blkPaddr"
-  - "wire [7:0] _prefetchMSHRs_7_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_6_io_req_ready"
   - "wire _prefetchMSHRs_6_io_acquire_valid"
-  - "wire [41:0] _prefetchMSHRs_6_io_resp_bits_blkPaddr"
-  - "wire [7:0] _prefetchMSHRs_6_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_5_io_req_ready"
   - "wire _prefetchMSHRs_5_io_acquire_valid"
-  - "wire [41:0] _prefetchMSHRs_5_io_resp_bits_blkPaddr"
-  - "wire [7:0] _prefetchMSHRs_5_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_4_io_req_ready"
   - "wire _prefetchMSHRs_4_io_acquire_valid"
-  - "wire [41:0] _prefetchMSHRs_4_io_resp_bits_blkPaddr"
-  - "wire [7:0] _prefetchMSHRs_4_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_3_io_req_ready"
   - "wire _prefetchMSHRs_3_io_acquire_valid"
-  - "wire [41:0] _prefetchMSHRs_3_io_resp_bits_blkPaddr"
-  - "wire [7:0] _prefetchMSHRs_3_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_2_io_req_ready"
   - "wire _prefetchMSHRs_2_io_acquire_valid"
-  - "wire [41:0] _prefetchMSHRs_2_io_resp_bits_blkPaddr"
-  - "wire [7:0] _prefetchMSHRs_2_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_1_io_req_ready"
   - "wire _prefetchMSHRs_1_io_acquire_valid"
-  - "wire [41:0] _prefetchMSHRs_1_io_resp_bits_blkPaddr"
-  - "wire [7:0] _prefetchMSHRs_1_io_resp_bits_vSetIdx"
   - "wire _prefetchMSHRs_0_io_req_ready"
   - "wire _prefetchMSHRs_0_io_acquire_valid"
-  - "wire [41:0] _prefetchMSHRs_0_io_resp_bits_blkPaddr"
-  - "wire [7:0] _prefetchMSHRs_0_io_resp_bits_vSetIdx"
 
   - "wire _fetchMSHRs_3_io_req_ready"
   - "wire _fetchMSHRs_3_io_acquire_valid"
-  - "wire [41:0] _fetchMSHRs_3_io_resp_bits_blkPaddr"
-  - "wire [7:0] _fetchMSHRs_3_io_resp_bits_vSetIdx"
   - "wire _fetchMSHRs_2_io_req_ready"
   - "wire _fetchMSHRs_2_io_acquire_valid"
-  - "wire [41:0] _fetchMSHRs_2_io_resp_bits_blkPaddr"
-  - "wire [7:0] _fetchMSHRs_2_io_resp_bits_vSetIdx"
   - "wire _fetchMSHRs_1_io_req_ready"
   - "wire _fetchMSHRs_1_io_acquire_valid"
-  - "wire [41:0] _fetchMSHRs_1_io_resp_bits_blkPaddr"
-  - "wire [7:0] _fetchMSHRs_1_io_resp_bits_vSetIdx"
   - "wire _fetchMSHRs_0_io_req_ready"
   - "wire _fetchMSHRs_0_io_acquire_valid"
-  - "wire [41:0] _fetchMSHRs_0_io_resp_bits_blkPaddr"
-  - "wire [7:0] _fetchMSHRs_0_io_resp_bits_vSetIdx"
 
-  - "wire _prefetchDemux_io_chosen"
-  - "wire _prefetchDemux_io_in_ready"
-  - "wire _prefetchDemux_io_in_valid_T_1"
-  - "wire _fetchDemux_io_in_ready"
-  - "wire _fetchDemux_io_in_valid_T_1"
-
-  - "wire prefetchHit"
-  - "wire fetchHit"
-
-  - "wire last_fire"
-  - "reg last_fire_r"
-
-  - "wire _priorityFIFO_io_enq_ready"
-  - "wire _priorityFIFO_io_enq_valid_T_probe"
-  - "wire _priorityFIFO_io_deq_valid"
-  - "wire _priorityFIFO_io_deq_ready_T"
-  - "wire _priorityFIFO_io_deq_bits"

ut_frontend/icache/missunit/agent/missunit_agent.py

@@ -160,7 +160,9 @@ async def drive_respond_with_grant(self,
                                data_beats: list,
                                beat_size_code: int = 6,
                                op_code: int = 5,
-                               is_corrupt_list: list = None
+                               is_corrupt_list: list = None,
+                               pre_beat_hook=None,
+                               post_beat_hook=None
                               ):
         num_beats = len(data_beats)
         if is_corrupt_list is None:
@@ -182,9 +184,14 @@ async def drive_respond_with_grant(self,
             self.bundle.io._mem._grant._valid.value = 1
 
             toffee.info(f"Sending Grant beat {i+1}/{num_beats}: data={hex(current_beat_data)}, corrupt={current_corrupt}")
+            if pre_beat_hook is not None:
+                await pre_beat_hook(i)
+            await self.bundle.step()
+            if post_beat_hook is not None:
+                await post_beat_hook(i)
+            self.bundle.io._mem._grant._valid.value = 0
             await self.bundle.step()
 
-        self.bundle.io._mem._grant._valid.value = 0
         toffee.info(f"Grant transmission finished for source_id={source_id}.")
 
     async def drive_get_fetch_response(self, timeout_cycles: int = 20) -> dict | None:
@@ -204,4 +211,4 @@ async def drive_get_fetch_response(self, timeout_cycles: int = 20) -> dict | Non
             await self.bundle.step()
 
         toffee.info(f"Timeout: Did not capture fetch response after {timeout_cycles} cycles.")
-        return None
+        return None

ut_frontend/icache/missunit/bundle/missunit_bundle.py

@@ -2,7 +2,6 @@
 
 class _0Bundle(Bundle):
 	_acquire_valid, _req_ready = Signals(2)
-	_resp_bits_blkPaddr, _resp_bits_vSetIdx = Signals(2)
 
 class _1Bundle(Bundle):
 	_io = _0Bundle.from_prefix("_io")
@@ -28,8 +27,6 @@ class _3Bundle(Bundle):
 class _4Bundle(Bundle):
 	_prefetchMSHRs = _3Bundle.from_prefix("_prefetchMSHRs")
 	_fetchMSHRs = _2Bundle.from_prefix("_fetchMSHRs")
-	last_fire_r, last_fire = Signals(2)
-	fetchHit, prefetchHit = Signals(2)
 
 class _5Bundle(Bundle):
 	_data, _virIdx, _waymask = Signals(3)
@@ -62,7 +59,6 @@ class _12Bundle(Bundle):
 class _13Bundle(Bundle):
 	_bits = _12Bundle.from_prefix("_bits")
 	_valid, _ready = Signals(2)
-	_valid_T_probe,_ready_T = Signals(2) 
 
 class _14Bundle(Bundle):
 	_source, _corrupt, _data, _size, _opcode = Signals(5)
@@ -98,19 +94,7 @@ class _21Bundle(Bundle):
 	_prefetch_req = _8Bundle.from_prefix("_prefetch_req")
 	_fencei, _flush, _hartId = Signals(3)
 
-class _22Bundle(Bundle):
-	_io_enq = _13Bundle.from_prefix("_io_enq")
-	_io_deq = _13Bundle.from_prefix("_io_deq")
-	_io_deq_bits = Signal()
-
-
-class _24Bundle(Bundle):
-	_io_chosen, _io_in_ready, _io_in_valid_T_1 = Signals(3)
-
 class ICacheMissUnitBundle(Bundle):
 	io = _21Bundle.from_prefix("io")
-	priorityFIFO = _22Bundle.from_prefix("ICacheMissUnit__priorityFIFO")
 	ICacheMissUnit_ = _4Bundle.from_prefix("ICacheMissUnit_")
-	prefetchDemux = _24Bundle.from_prefix("ICacheMissUnit__prefetchDemux")
-	fetchDemux = _24Bundle.from_prefix("ICacheMissUnit__fetchDemux")
 	reset, clock = Signals(2)