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Merged
miceforrat merged 1 commit into from
Feb 25, 2026
Merged

ifu top ref and env test added #192

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320 changes: 319 additions & 1 deletion scripts/ifu_related/ifu_top_internals.yaml
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Original file line number Diff line number Diff line change
@@ -1,4 +1,322 @@
NewIFU:
# - "wire f1_flush"
- "wire f2_flush"
- "wire f3_flush"
- "wire f3_flush"
- "wire f1_ready"
- "wire f1_valid"
- "wire wb_enable"
- "wire f1_fire"
- "wire f0_fire"
- "wire f2_ready"
- "wire f3_ready"
- "wire f2_fire"
- "wire f2_valid"
- "wire f3_valid"
- "wire f2_icache_all_resp_wire"
- "wire f2_icache_all_resp_reg"
- "wire icacheRespAllValid"
- "wire f0_flush_from_bpu_probe"
- "wire [1:0] f2_exception_0"
- "wire [1:0] f2_exception_1"
- "wire is_first_instr"
- "reg f3_lastHalf_valid"
- "reg [3:0] mmio_state"
- "reg [1:0] f3_exception_vec_0"
- "reg [1:0] f3_exception_vec_1"
- "reg [1:0] f3_exception_vec_2"
- "reg [1:0] f3_exception_vec_3"
- "reg [1:0] f3_exception_vec_4"
- "reg [1:0] f3_exception_vec_5"
- "reg [1:0] f3_exception_vec_6"
- "reg [1:0] f3_exception_vec_7"
- "reg [1:0] f3_exception_vec_8"
- "reg [1:0] f3_exception_vec_9"
- "reg [1:0] f3_exception_vec_10"
- "reg [1:0] f3_exception_vec_11"
- "reg [1:0] f3_exception_vec_12"
- "reg [1:0] f3_exception_vec_13"
- "reg [1:0] f3_exception_vec_14"
- "reg [1:0] f3_exception_vec_15"
- "reg [6:0] f2_cut_ptr_0"
- "reg [6:0] f2_cut_ptr_1"
- "reg [6:0] f2_cut_ptr_2"
- "reg [6:0] f2_cut_ptr_3"
- "reg [6:0] f2_cut_ptr_4"
- "reg [6:0] f2_cut_ptr_5"
- "reg [6:0] f2_cut_ptr_6"
- "reg [6:0] f2_cut_ptr_7"
- "reg [6:0] f2_cut_ptr_8"
- "reg [6:0] f2_cut_ptr_9"
- "reg [6:0] f2_cut_ptr_10"
- "reg [6:0] f2_cut_ptr_11"
- "reg [6:0] f2_cut_ptr_12"
- "reg [6:0] f2_cut_ptr_13"
- "reg [6:0] f2_cut_ptr_14"
- "reg [6:0] f2_cut_ptr_15"
- "reg [6:0] f2_cut_ptr_16"
- "reg [49:0] f3_pc_0"
- "reg [49:0] f3_pc_1"
- "reg [49:0] f3_pc_2"
- "reg [49:0] f3_pc_3"
- "reg [49:0] f3_pc_4"
- "reg [49:0] f3_pc_5"
- "reg [49:0] f3_pc_6"
- "reg [49:0] f3_pc_7"
- "reg [49:0] f3_pc_8"
- "reg [49:0] f3_pc_9"
- "reg [49:0] f3_pc_10"
- "reg [49:0] f3_pc_11"
- "reg [49:0] f3_pc_12"
- "reg [49:0] f3_pc_13"
- "reg [49:0] f3_pc_14"
- "reg [49:0] f3_pc_15"
- "reg [47:0] f3_paddrs_0"
- "reg [55:0] f3_gpaddr"
- "wire [15:0] f3_instr_range"
# - "wire mmioFlushWb_bits_pd_0_isRVC"
# - "wire mmioFlushWb_bits_pd_0_brType"
# - "wire mmioFlushWb_bits_pd_0_isRet"
# - "wire mmioFlushWb_bits_pd_0_isCall"

- preDecoder:
- "wire [15:0] io_in_bits_data_0"
- "wire [15:0] io_in_bits_data_1"
- "wire [15:0] io_in_bits_data_2"
- "wire [15:0] io_in_bits_data_3"
- "wire [15:0] io_in_bits_data_4"
- "wire [15:0] io_in_bits_data_5"
- "wire [15:0] io_in_bits_data_6"
- "wire [15:0] io_in_bits_data_7"
- "wire [15:0] io_in_bits_data_8"
- "wire [15:0] io_in_bits_data_9"
- "wire [15:0] io_in_bits_data_10"
- "wire [15:0] io_in_bits_data_11"
- "wire [15:0] io_in_bits_data_12"
- "wire [15:0] io_in_bits_data_13"
- "wire [15:0] io_in_bits_data_14"
- "wire [15:0] io_in_bits_data_15"
- "wire [15:0] io_in_bits_data_16"
- "wire io_out_pd_0_isRVC"
- "wire io_out_pd_1_valid"
- "wire io_out_pd_1_isRVC"
- "wire io_out_pd_2_valid"
- "wire io_out_pd_2_isRVC"
- "wire io_out_pd_3_valid"
- "wire io_out_pd_3_isRVC"
- "wire io_out_pd_4_valid"
- "wire io_out_pd_4_isRVC"
- "wire io_out_pd_5_valid"
- "wire io_out_pd_5_isRVC"
- "wire io_out_pd_6_valid"
- "wire io_out_pd_6_isRVC"
- "wire io_out_pd_7_valid"
- "wire io_out_pd_7_isRVC"
- "wire io_out_pd_8_valid"
- "wire io_out_pd_8_isRVC"
- "wire io_out_pd_9_valid"
- "wire io_out_pd_9_isRVC"
- "wire io_out_pd_10_valid"
- "wire io_out_pd_10_isRVC"
- "wire io_out_pd_11_valid"
- "wire io_out_pd_11_isRVC"
- "wire io_out_pd_12_valid"
- "wire io_out_pd_12_isRVC"
- "wire io_out_pd_13_valid"
- "wire io_out_pd_13_isRVC"
- "wire io_out_pd_14_valid"
- "wire io_out_pd_14_isRVC"
- "wire io_out_pd_15_valid"
- "wire io_out_pd_15_isRVC"
- "wire io_out_hasHalfValid_2"
- "wire io_out_hasHalfValid_3"
- "wire io_out_hasHalfValid_4"
- "wire io_out_hasHalfValid_5"
- "wire io_out_hasHalfValid_6"
- "wire io_out_hasHalfValid_7"
- "wire io_out_hasHalfValid_8"
- "wire io_out_hasHalfValid_9"
- "wire io_out_hasHalfValid_10"
- "wire io_out_hasHalfValid_11"
- "wire io_out_hasHalfValid_12"
- "wire io_out_hasHalfValid_13"
- "wire io_out_hasHalfValid_14"
- "wire io_out_hasHalfValid_15"
- "reg [31:0] io_out_instr_0"
- "reg [31:0] io_out_instr_1"
- "reg [31:0] io_out_instr_2"
- "reg [31:0] io_out_instr_3"
- "reg [31:0] io_out_instr_4"
- "reg [31:0] io_out_instr_5"
- "reg [31:0] io_out_instr_6"
- "reg [31:0] io_out_instr_7"
- "reg [31:0] io_out_instr_8"
- "reg [31:0] io_out_instr_9"
- "reg [31:0] io_out_instr_10"
- "reg [31:0] io_out_instr_11"
- "reg [31:0] io_out_instr_12"
- "reg [31:0] io_out_instr_13"
- "reg [31:0] io_out_instr_14"
- "reg [31:0] io_out_instr_15"
- "reg [63:0] io_out_jumpOffset_0"
- "reg [63:0] io_out_jumpOffset_1"
- "reg [63:0] io_out_jumpOffset_2"
- "reg [63:0] io_out_jumpOffset_3"
- "reg [63:0] io_out_jumpOffset_4"
- "reg [63:0] io_out_jumpOffset_5"
- "reg [63:0] io_out_jumpOffset_6"
- "reg [63:0] io_out_jumpOffset_7"
- "reg [63:0] io_out_jumpOffset_8"
- "reg [63:0] io_out_jumpOffset_9"
- "reg [63:0] io_out_jumpOffset_10"
- "reg [63:0] io_out_jumpOffset_11"
- "reg [63:0] io_out_jumpOffset_12"
- "reg [63:0] io_out_jumpOffset_13"
- "reg [63:0] io_out_jumpOffset_14"
- "reg [63:0] io_out_jumpOffset_15"
- f3Predecoder:
- "reg [1:0] io_out_pd_0_brType"
- "wire io_out_pd_0_isCall"
- "wire io_out_pd_0_isRet"
- "reg [1:0] io_out_pd_1_brType"
- "wire io_out_pd_1_isCall"
- "wire io_out_pd_1_isRet"
- "reg [1:0] io_out_pd_2_brType"
- "wire io_out_pd_2_isCall"
- "wire io_out_pd_2_isRet"
- "reg [1:0] io_out_pd_3_brType"
- "wire io_out_pd_3_isCall"
- "wire io_out_pd_3_isRet"
- "reg [1:0] io_out_pd_4_brType"
- "wire io_out_pd_4_isCall"
- "wire io_out_pd_4_isRet"
- "reg [1:0] io_out_pd_5_brType"
- "wire io_out_pd_5_isCall"
- "wire io_out_pd_5_isRet"
- "reg [1:0] io_out_pd_6_brType"
- "wire io_out_pd_6_isCall"
- "wire io_out_pd_6_isRet"
- "reg [1:0] io_out_pd_7_brType"
- "wire io_out_pd_7_isCall"
- "wire io_out_pd_7_isRet"
- "reg [1:0] io_out_pd_8_brType"
- "wire io_out_pd_8_isCall"
- "wire io_out_pd_8_isRet"
- "reg [1:0] io_out_pd_9_brType"
- "wire io_out_pd_9_isCall"
- "wire io_out_pd_9_isRet"
- "reg [1:0] io_out_pd_10_brType"
- "wire io_out_pd_10_isCall"
- "wire io_out_pd_10_isRet"
- "reg [1:0] io_out_pd_11_brType"
- "wire io_out_pd_11_isCall"
- "wire io_out_pd_11_isRet"
- "reg [1:0] io_out_pd_12_brType"
- "wire io_out_pd_12_isCall"
- "wire io_out_pd_12_isRet"
- "reg [1:0] io_out_pd_13_brType"
- "wire io_out_pd_13_isCall"
- "wire io_out_pd_13_isRet"
- "reg [1:0] io_out_pd_14_brType"
- "wire io_out_pd_14_isCall"
- "wire io_out_pd_14_isRet"
- "reg [1:0] io_out_pd_15_brType"
- "wire io_out_pd_15_isCall"
- "wire io_out_pd_15_isRet"

- predChecker:
- "wire io_in_instrValid_0"
- "wire io_in_instrValid_1"
- "wire io_in_instrValid_2"
- "wire io_in_instrValid_3"
- "wire io_in_instrValid_4"
- "wire io_in_instrValid_5"
- "wire io_in_instrValid_6"
- "wire io_in_instrValid_7"
- "wire io_in_instrValid_8"
- "wire io_in_instrValid_9"
- "wire io_in_instrValid_10"
- "wire io_in_instrValid_11"
- "wire io_in_instrValid_12"
- "wire io_in_instrValid_13"
- "wire io_in_instrValid_14"
- "wire io_in_instrValid_15"
- "wire io_out_stage1Out_fixedRange_0"
- "wire io_out_stage1Out_fixedRange_1"
- "wire io_out_stage1Out_fixedRange_2"
- "wire io_out_stage1Out_fixedRange_3"
- "wire io_out_stage1Out_fixedRange_4"
- "wire io_out_stage1Out_fixedRange_5"
- "wire io_out_stage1Out_fixedRange_6"
- "wire io_out_stage1Out_fixedRange_7"
- "wire io_out_stage1Out_fixedRange_8"
- "wire io_out_stage1Out_fixedRange_9"
- "wire io_out_stage1Out_fixedRange_10"
- "wire io_out_stage1Out_fixedRange_11"
- "wire io_out_stage1Out_fixedRange_12"
- "wire io_out_stage1Out_fixedRange_13"
- "wire io_out_stage1Out_fixedRange_14"
- "wire io_out_stage1Out_fixedRange_15"
- "wire io_out_stage1Out_fixedTaken_0"
- "wire io_out_stage1Out_fixedTaken_1"
- "wire io_out_stage1Out_fixedTaken_2"
- "wire io_out_stage1Out_fixedTaken_3"
- "wire io_out_stage1Out_fixedTaken_4"
- "wire io_out_stage1Out_fixedTaken_5"
- "wire io_out_stage1Out_fixedTaken_6"
- "wire io_out_stage1Out_fixedTaken_7"
- "wire io_out_stage1Out_fixedTaken_8"
- "wire io_out_stage1Out_fixedTaken_9"
- "wire io_out_stage1Out_fixedTaken_10"
- "wire io_out_stage1Out_fixedTaken_11"
- "wire io_out_stage1Out_fixedTaken_12"
- "wire io_out_stage1Out_fixedTaken_13"
- "wire io_out_stage1Out_fixedTaken_14"
- "wire io_out_stage1Out_fixedTaken_15"
- "reg [49:0] io_out_stage2Out_fixedTarget_0"
- "reg [49:0] io_out_stage2Out_fixedTarget_1"
- "reg [49:0] io_out_stage2Out_fixedTarget_2"
- "reg [49:0] io_out_stage2Out_fixedTarget_3"
- "reg [49:0] io_out_stage2Out_fixedTarget_4"
- "reg [49:0] io_out_stage2Out_fixedTarget_5"
- "reg [49:0] io_out_stage2Out_fixedTarget_6"
- "reg [49:0] io_out_stage2Out_fixedTarget_7"
- "reg [49:0] io_out_stage2Out_fixedTarget_8"
- "reg [49:0] io_out_stage2Out_fixedTarget_9"
- "reg [49:0] io_out_stage2Out_fixedTarget_10"
- "reg [49:0] io_out_stage2Out_fixedTarget_11"
- "reg [49:0] io_out_stage2Out_fixedTarget_12"
- "reg [49:0] io_out_stage2Out_fixedTarget_13"
- "reg [49:0] io_out_stage2Out_fixedTarget_14"
- "reg [49:0] io_out_stage2Out_fixedTarget_15"
- "reg [49:0] io_out_stage2Out_jalTarget_0"
- "reg [49:0] io_out_stage2Out_jalTarget_1"
- "reg [49:0] io_out_stage2Out_jalTarget_2"
- "reg [49:0] io_out_stage2Out_jalTarget_3"
- "reg [49:0] io_out_stage2Out_jalTarget_4"
- "reg [49:0] io_out_stage2Out_jalTarget_5"
- "reg [49:0] io_out_stage2Out_jalTarget_6"
- "reg [49:0] io_out_stage2Out_jalTarget_7"
- "reg [49:0] io_out_stage2Out_jalTarget_8"
- "reg [49:0] io_out_stage2Out_jalTarget_9"
- "reg [49:0] io_out_stage2Out_jalTarget_10"
- "reg [49:0] io_out_stage2Out_jalTarget_11"
- "reg [49:0] io_out_stage2Out_jalTarget_12"
- "reg [49:0] io_out_stage2Out_jalTarget_13"
- "reg [49:0] io_out_stage2Out_jalTarget_14"
- "reg [49:0] io_out_stage2Out_jalTarget_15"
- "reg [2:0] io_out_stage2Out_faultType_0_value"
- "reg [2:0] io_out_stage2Out_faultType_1_value"
- "reg [2:0] io_out_stage2Out_faultType_2_value"
- "reg [2:0] io_out_stage2Out_faultType_3_value"
- "reg [2:0] io_out_stage2Out_faultType_4_value"
- "reg [2:0] io_out_stage2Out_faultType_5_value"
- "reg [2:0] io_out_stage2Out_faultType_6_value"
- "reg [2:0] io_out_stage2Out_faultType_7_value"
- "reg [2:0] io_out_stage2Out_faultType_8_value"
- "reg [2:0] io_out_stage2Out_faultType_9_value"
- "reg [2:0] io_out_stage2Out_faultType_10_value"
- "reg [2:0] io_out_stage2Out_faultType_11_value"
- "reg [2:0] io_out_stage2Out_faultType_12_value"
- "reg [2:0] io_out_stage2Out_faultType_13_value"
- "reg [2:0] io_out_stage2Out_faultType_14_value"
- "reg [2:0] io_out_stage2Out_faultType_15_value"
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