Partitioner Feature Additions: Mapping generation, net-span partition report, LUTs/partition report, verbose hypergraph reports, LUTCount CLI, mapping constraint partition input by pnewlin-amd · Pull Request #1343 · Xilinx/RapidWright

pnewlin-amd · 2026-01-05T17:20:25Z

A series of QoL features and additions to the partitioner branch.

Added hierarchical mapping output (mapping.txt), if an entire submodule TOP/Counter is wholly contained in partition 1 (FPGA_B) then produce only one line TOP/Counter FPGA_B
Added optional human readable hypergraph reports. After a partition a user can easily see which nets have been cut and their names.
Added a dedicated LUT report .txt file output which shows how many LUTs have been assigned per partition.
Exposed KaHyPar hypergraph switches to command line interface
Added partition constraints, this allows the user to specify a mapping constraint which KaHyPar will interpret as a .fix input for assigning some submodule to exactly one partition.
Changed partition naming to be FPGA_<...>.
Added a cells.txt output which displays every partition name.
Added command line interface option to specify output location of partition.
Relocated the LUT counting functionality to a single location (source of truth)
Added verbose logging to partition process to display caught edge cases and memory usage.
Enabled KaHyPar verbose timing output.
Added partition support for .DCP input.
Added read netlist command line interface tool. Allows user to test memory usage on monolithic netlists.
Added LUT count command line interface tool. Allows user to provide a netlist and RapidWright will return total LUT count of top level.

…partition report, human readable hypergraph reports Signed-off-by: Perry Newlin <perry.newlin@amd.com>

clavin-xlnx

First round of feedback, please reach out with questions. I didn't make comments on every occurrence, but hopefully you'll be able to apply the patterns across all the changes.

Thanks for the PR!

clavin-xlnx · 2026-01-06T17:01:29Z

+/**
+ * Memory audit utility for reading netlists.
+ */
+public class ReadNetlist {


This class seems to duplicate functionality in the CodePerfTracker class. This class is employed when loading a DCP and, when set with the right options, can produce a similar report. When calling Design.readCheckpoint() there are overload options to provide a custom configured CodePerfTracker instance. Have a look to see if that would meet your needs.

I'm thinking that having something like a DesignAnalyzer that can provide an array of analysis options while simply loading a design would be useful, but I'm not sure this is the right PR for it.

clavin-xlnx · 2026-01-06T17:06:59Z

+     * - counts: aggregated counts over this node’s subtree (leafCounts + all children)
+     *           lets us easily decide if wholly contained or not
+     */
+    private static final class Node {


Node is an overloaded term. Perhaps we could refactor to something more unique such as HierNode, or something similar.

clavin-xlnx · 2026-01-06T17:11:45Z

+/**
+ * CLI utility to count logic LUT usage from EDIF (.edf/.edif) or Vivado DCP (.dcp).
+ */
+public final class LUTCount {


I think the functionality of this class should be absorbed into a DesignAnalyzer class. See my comment on ReadNetlist.java.

clavin-xlnx · 2026-01-06T17:14:28Z

+                Files.createDirectories(parent);
+            }
+            Files.write(out, lines, StandardCharsets.UTF_8);
+        } catch (IOException e) { // more guards the better.


Not sure what you mean by this comment?

clavin-xlnx · 2026-01-06T17:18:20Z

+     * @param partitions A map of partition IDs to sets of instance names.
+     * @param instLutCountMap A map of instance LUT counts (unused but kept for API consistency).
+     */
+    public static void write(Path outDir


This method is confusingly named as the Javadoc says it writes the mapping file, but there is a method just above it that is called writeMappingFile().

clavin-xlnx · 2026-01-06T21:29:23Z

+
+
+


Remove extra whitespace.

clavin-xlnx · 2026-01-06T21:30:03Z

+
+
+        // ============================================================================
+        // ARGUMENT PARSING & INITIALIZATION


It seems like main() is broken up into various tasks, but they are all in the same method (its over 700 lines long). This should be broken up into separate methods.

Good point. Next commit will include PartitionSolutionProcessor.java all of the processing and artifact generation (mapping.txt, lut_report.txt, etc.) that occurs after the KaHyPar partition solution is found will be moved into this file. Partitioner.java will utilize these functions.

Going to move netlist coarsening and edge discovery code into partitiontools.java.

Partitioner.java is sitting at ~400lines on my side right now, hopefully this next commit makes organization much easier to follow.

clavin-xlnx · 2026-01-06T21:30:55Z

+            int backfillAttempts = 0;
+            int backfillSuccess = 0;
+            int backfillSkipped = 0;
+            java.util.Map<com.xilinx.rapidwright.edif.EDIFCell, java.lang.Integer> lutCountCache;


Please avoid fully qualified references and instead just import the class at the top of the file.

clavin-xlnx · 2026-01-06T21:34:37Z

@@ -0,0 +1,62 @@
+/*


Not sure if this functionality needs its own class. Perhaps refactor to make it a bit more generic and put it in StringTools?

clavin-xlnx · 2026-01-06T21:38:36Z

+            String partitionLabelB = pairKey.substring(separatorIndex + 1);
+            int pairCount = pairCounts.get(pairKey);
+
+            //format will be "FPGA_A--count--FPGA_B".


Suggested change

//format will be "FPGA_A--count--FPGA_B".

// format will be "FPGA_A--count--FPGA_B".

…add 'fpga_io_cuts' report which considers directionality Signed-off-by: Perry Newlin <perry.newlin@amd.com>

Partitioner: Mapping generation, net-span report (io cuts), LUTs per …

0191cd6

…partition report, human readable hypergraph reports Signed-off-by: Perry Newlin <perry.newlin@amd.com>

clavin-xlnx requested changes Jan 6, 2026

View reviewed changes

update hMETIS file to default to fmt=10, considering vertex weights. …

aae7185

…add 'fpga_io_cuts' report which considers directionality Signed-off-by: Perry Newlin <perry.newlin@amd.com>

pnewlin-amd force-pushed the partitioner-squashed branch from 5550198 to aae7185 Compare January 12, 2026 15:56

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Partitioner Feature Additions: Mapping generation, net-span partition report, LUTs/partition report, verbose hypergraph reports, LUTCount CLI, mapping constraint partition input#1343

Partitioner Feature Additions: Mapping generation, net-span partition report, LUTs/partition report, verbose hypergraph reports, LUTCount CLI, mapping constraint partition input#1343
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		// ============================================================================
		// ARGUMENT PARSING & INITIALIZATION

	//format will be "FPGA_A--count--FPGA_B".
	// format will be "FPGA_A--count--FPGA_B".

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